I admit it, I get a high when meeting customers and hearing how they are using our tools. It is a pleasure to see that we are really helping them improve their efficiency and ultimately their lives. That’s gotta be a reward in itself for anyone.

Its not always perfect though, once in a while a customer will give it to me that there are issues and we need to address them immediately. I like to take that on the chin. I think the best way to take feedback is for the CEO (that would be me in this case) to hear the music first hand. Of course this is not possible for large companies, or maybe it is for their large multimillion dollar customers. We are not that large – yet.

Beautiful snow cap mountains on the way to DVCon

At the recent DVCon, at the Accellera “Town hall” luncheon meeting I raised the question about “who is looking out for the needs of the mid to small size semiconductor companies”. You see standards are created by Accellera and I see that a lot of big companies have the resources to send and attend these meetings and drive their perspective. I feel that SMB – a lot of our customers – are not represented at these Accellera meetings.

Bill Gates questions why it is that treatment for Hair loss receives more funding than Malaria.

I suspect we could get standards that are good for the large corporations and could be a real pain in the a** for small and mid-sized ones.

At one of the lunches hosted at the DVCon show, I got into an interesting discussion with the Editor of EE Journal (Kevin Moris) about what motivates people to act (buy): Fear and greed. EDA companies use that all the time – “Use our tools because successful companies are doing so …”

Proof that Agnisys was there!

I was interviewed by Amelia Dalton for her pod cast “Fish Fry” which I really enjoyed.  And later by Graham Bell for EDACafe.

At this year’s DVCon our booth was well attended. We also announced the free Register Generator for UVM. This, might I add, is selling like crazy

So the cat is out of the bag. We are working on an assertion tool. This DVCon we turned quite a few heads when we announced our new assertion product IAssertSpec. Not that the tool is ready by any stretch of the imagination, we wanted to gauge the interest of the user community. We wanted to see if people were interested in getting some help with assertions. So we first asked some help overselves from the experts in the field Ben Cohen and Srini, who have even written a few books on Assertions. 
With their help, we created a quiz and invited web visitors and our DVCon booth visitors to take it. I don’t know what was intimidating about the quiz but not many people who came to the booth attempted it. For those that attempted it took more than 10 minutes to complete the 10 multiple choice questions. It wasn’t that people did not know assertions, they were literally scared of assertions or perhaps being judged.

I will be the first to admit that there were at least a couple of issues with the quiz (which have since then been fixed). However, only 5% scored a perfect 10. Spoiler alert – the correct answers of the quiz are here.

We believe that this quiz and its results validates our premise that assertions are too difficult to create, understand and manage. Sure there will be a few individuals in every company who understand them inside and out. However, what about the rest? Should they just be at the mercy of the experts? Should they drop everything else, role up their sleeves and try and learn assertions or get one of the available (or soon to be available) tools to help with the assertions? The newer assertion syntax (IEEE 1800-2009) will only exacerbate the problem because it is even more complex.

We feel that assertion productivity tools have a very important role to play in promoting a more widespread use of assertions. They will make assertions ubiquitous and less scary.
Come back to check more updates from us on this new tool. Meanwhile request a login account here to see the latest IAssertSpec.

Its heartening to see greater cooperation between various EDA companies, both big and small. The ongoing work under Accellera for UVM, UCIS and IP-XACT is testament to this fact.  It is often bemusing to see the push and pull in the Accellera technical meetings between the members. However, in the end greater sense typically prevails and as a result the industry as a whole is moving towards achieving something that’s greater than the sum of its parts. What Accellera is doing now will go a long way in achieving its goal of improving designer’s productivity through worldwide development and use of standards.

Collaboration isn’t just limited to Accellera, we are thrilled that Cadence has included us in their Verification Alliance Partner program. This completes our goal to partner with the three major EDA tools vendors – Mentor, Synopsys and now Cadence. We are grateful to these companies for trusting us with their valuable tools and promoting innovation and enterprise. We will continue to work with our common customers and create greater value for them.

In continuation of the collaboration theme, we too have started a new program called Agnisys Fusion Partner Program. This program is open to companies and individuals who are engaged in providing services/training for the Semiconductor industry.

We look forward to working with our ecosystem partners and in the words of Cadence’s CMO, close the “Profitability Gap” in the electronics industry.

Hardware design verification consumes more than 60% of resources, often more than that. These resources are not just engineers but also time, machines and licenses.

Speeding-up regression run-time not only reduces the time to achieve verification closure, but also reduces the need for additional EDA licenses, and the pressure for additional compute power.  So how do you go about doing that?

Here are a few tips to reduce the regression run-times for any verification environment :

1. Are you in the right forest? It seems obvious, but none the less, a good place to start is to make sure you have the right set of tests in your regression suite. This question takes you back to the verification plan and all the way back to the functional specification of the design. There is no point verifying functionality that has been removed or modified. I happen to talk to a verification manager at a large semiconductor company recently and he told me his team was so focused on improving coverage of their verification suite that they were shocked when they found out that the specs had changed and they were not in the loop.

2. A list for every occasion! : Create multiple regression lists so that users can choose the most appropriate one to run. Share these lists with the design and verification team. Here are a few ideas on which lists to create …

• Qualifying regression list : Contains tests that will be run by all designers to make sure they are making forward progress and have not broken any functionality.
• Function based regression list : Have a regression list for each function group so that various aspects of the design can be verified.
• Comprehensive regression list : This is the integration regression list which is the kitchen-sink of all tests. This is run periodically – say very night or every weekend.

Having an appropriate regression list ensures just the optimum tests are run without causing any waste. The Qualifying regression is the one that will be run the most often so it better be as succinct as possible, while covering major functional sections.

3. Fine-tune the regressions : Remove redundant tests from the regression lists and reduce run time for tests. This can be done in the following ways …

• Comparing historic test results. If two tests have the same “result signature” (same pass/fail status) from the past, then only one need to be in the Qualifying regression set. Which one is chosen can be based on their respective run times. Obviously, the shorter the run time the better.
• Often tests can be made faster by using techniques such as back-door loads for configuration registers, using special simulation oriented configurations (e.g. use a shorter frame size, shorter time-out values etc.)
• Use coverage based test ranking. Almost all good simulators give the ability to rank the tests, this can be used to choose the most appropriate tests.

4. Run only if needed : Use the dependency management in load management systems (e.g. LSF) to run tests based on the results of other tests. For example, if the basic Reset tests fail, no need to run any other functional tests, or if functional tests fail, no need to run the low-power tests, and so on.

5. Vote for a systematic approach : Use a systematic method to manage all regressions and their results. Good analysis of current and historic regression results significantly reduces regressions themselves and gets to faster verification closure – the holy grail of verification teams.

These tips can be adopted in an ad hoc manner or you can use IVerifySpec for regression and verification management. In our experience, using these techniques one can cut down on regression run times anywhere from 25-50%.

What has your experience been, how have you reduced your regression run-times?

We almost didn’t go to DAC this year, and that would have been a big mistake. Monday started out with one of our biggest competitor dropping by to say hello and get demos of our products. The remaining competitors also dropped by later. Maybe we can work together after all.

Over the course of DAC exhibit days, we had several large semiconductor companies drop by and we were in strategic meetings with some of our partners. This was great, since there is no other time or place one would get so much density of action. DAC is great for startups and we have already signed up for the next year.

At the Accellera sponsored breakfast about UVM/OVM it was nice to see a time line for register package (Oct 2010). We will of course follow it closely and come up with our implementation immediately. You really had to be there to see the collaborative/competitive nature of the meeting.

At my two talks at the UVM/Booth there was a decent turnout. For startups it is a great way to get more exposure. Thanks to Richard Brophy , Josef Derner @Mentor and Joe Hupcey @Cadence for organizing it.

Our IDesignSpec product for Register management wowed so many people, they were truly amazed at the ease of use and the innovative automation that it provides. Putting it on Xuropa also helped us spread the word. Due thanks to Harry the ASIC guy and James Colgen, CEO Xuropa.

Thanks to Chris, CTO @ GateRocket (picture below) who was available for the hour long poster presentation. There was interesting discussion about regression and verification management with some interested folks.

The BoF that I had tried to organize didn’t attract much attention. It was partly because of lack of sponsorship and time spent in advertising about it. I don’t think the subject of “Agile Verification Management” is stale. One indicator is that there is a lot of activity on the product development side at Mentor and Synopsys around verification management.

To our surprise, the problem of regression management is bigger than we had imagined and we feel that IVerifySpec is poised to satisfy the needs of a large number of users. There might even be a larger potential for this tool in other related areas.
This sure excites us to do more passionate development and deployment.

Started blogging again, this time from our own blogging site.

Its DAC time of the year again. This will be our 2nd year in a row at DAC. Hopefully we have learned from our mistakes and won’t be repeating them this year. DAC preparations are on full swing, with the entire Agnisys team working really hard and forgoing their summer lunch time siesta even

Apart from the usual DAC demos, we have two presentations scheduled at the OVM/UVM booth. Its gratifying that our two main tools (IDesignSpec and IVerifySpec) are in areas which are in great demand — Register Specification and Verification Management.

GateRocket, one of our long time customer, is presenting the results of their deployment of IVerifySpec™. GateRocket founder and CTO, Chris Schalick will present an overview of GateRocket’s use of IVerifySpec at a poster session entitled “Automation for Quality Improvements” to be held Wednesday, June 16, 2010, 1:30 PM — 2:30 PM, 2nd Floor Foyer Adjacent to 208AB.

We are also planning a Birds of a Feather session at DAC on JUNE 15, 2010 from 6:30pm-8:00pm. The topic is “Agile Verification Management” . See more details here.

All the printing material is in the press. We are preparing the gifts (all in one laser pen) and other goodies for the demo invites.

Hoping for yet another successful year at DAC. Time permitting I’ll be blogging from the DAC floor and subsequent road show to three cities.

See you there!

We had a great first day at DAC. All the talk about recession and economic doom were hard to believe. People were enthusiastic and upbeat. Even the guys and gals looking for work were upbeat and were considering it to be a temporary phase.

We started early at 6:00 AM from San Jose. The drive on Route 280 was nice in the morning with almost no traffic. Clouds on top of the hills along the way were very nice.

Reached at 7:00 and got down to setting up the three laptops and a (borrowed) projector. We had already setup the booth on Saturday.

Many interesting people doing cool things dropped by to see the products, many had seen us on Gary Smith and John Cooley’s must see list. Many others simply came with no idea what we were doing and to their surprise, they realized they could use our solutions.

Interestingly a few people thought that we were doing natural language parsing in IDesignSpec. Oh well, some day, at some DAC!