New Product Advances Productivity for SystemVerilog UVM Verification
Agnisys just released DVInsight-Pro version 2.0 with many new features that enable much more productive SV/UVM code development. Do you […]
October 27, 2023
Automating UVM-Based IP and SoC Functional Verification
Ask a bunch of engineers about the Universal Verification Methodology (UVM) and you’ll hear two distinct sets of responses, sometimes
Agnisys to Unveil Specta-AV at DAC 2019
BOSTON, MA – May 20, 2019 – Agnisys, Inc. to unveil Specta-AV™, a comprehensive UVM Testbench Generator for today’s IPs/SoCs,
Agnisys CEO Interview: Meet Anupam Bakshi
Although much of the EDA industry has consolidated into the “Big 3” players, there are still plenty of smaller vendors
Agnisys Announces Qualification for SoC Specification Automation Flow
Developers of Safety-Critical Vehicular Applications Can Deploy Solution with No Additional Tool Qualification Requirements Agnisys,Inc. the leading EDA provider of
Agnisys Unveils Software to Automate Register Verification Process
Lowell, MA. May 21, 2015 – Agnisys, Inc. announces immediate availability of ARV™ – Automatic Register Verification, an add-on product
Automating IP and SoC Development
The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed
AI Technology and FPGA Support for IP and SoC Specification Automation
New capabilities will be demonstrated at the Design Automation Conference (DAC) in San Francisco December 6-8 BOSTON, Mass. – December
Automatic Generation of SoC Verification Testbench and Tests
Last month, I blogged about a webinar on embedded systems development presented by Agnisys CEO and founder Anupam Bakshi. I liked the way that
