Tight Generator Interface support in SoC-E
Introduction As per the IP-XACT User Guide, IP-XACT defines an API called Tight Generator Interface (TGI) to query, modify, create, […]
November 16, 2023
Not your Average UVM Testbench Generator – Unveiling at DAC 2019
By Louie De Luna, Agnisys Chief Product Evangelist
An Update on Functional Safety and ISO 26262
Just about a year ago, I published a blog post about the emerging need for better functional safety and security
Automating Register Verification with 100% Functional Coverage
By Louie de Luna, Agnisys Director of Sales and Marketing
Semiconductor Data Sheet Automation – Just The Way You Want It
Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of
Next Gen SystemRDL: Implementing Registers with IDesignSpec
Typically thousands of registers are required for today’s complex designs, which are used to control the operations of the SOC.
Automating the UVM Register Abstraction Layer (RAL)
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology
What Every Engineer Should Know About SoC Register Generation
Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of registers and memory map elements. The design
