Custom IP Design and AI-Based Verification
Introduction Engineers have consistently strived to expedite ASIC development. Our latest endeavor at Agnisys introduces automation that captures specifications in […]
January 3, 2024
Three Smart Steps to Quickly Test a Register Map for Your Entire SoC
As I noted in a recent post, registers appear everywhere in system-on-chip (SoC) design. Architecturally defined registers form the hardware-software
Unlocking Efficiency in Semiconductor Design with the PSS Compiler by Agnisys
In the world of semiconductor design, where precision and efficiency are of utmost importance, the demand for streamlined methodologies is
Efficient Hardware Description: Transforming SystemRDL into Multiple Formats for Seamless Integration
The first and one of the most important steps of ASIC design flow is chip design specification. The specification can
