RTL, UVM and C Model & API Generation

Agnisys IDesignSpec™ (IDS) streamlines the design process by interactively generating comprehensive output files tailored for design, verification, software, and documentation teams. From your specifications, IDS produces a complete RTL description for registers and provision for memories, complete with bus slave and decode logic specific to user-selected bus protocols, along with any necessary clock-domain-crossing (CDC) synchronization logic. Supported interfaces include APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, Wishbone, and proprietary buses, enabling instant connectivity to the register bus. The generated RTL code—available in SystemVerilog, Verilog, VHDL, or SystemC—is human-readable and includes clear comments for easy integration with hand-written application logic RTL blocks and third-party IP for simulation and logic synthesis. 

The UVM Register Abstraction Layer model is auto-generated with complex functionalities, supporting access to registers through both bus interfaces and HDL paths, alongwith coverage and constraints management. Special register callback classes facilitate advanced features such as interrupt handling and parity checks.

For software development, IDS generates C headers in three flavors—structures and unions, macros, and optimized relocatable macros—as well as C++ headers for register groups and MISRA-compliant headers, complete with custom APIs for register read/write functions. This comprehensive generation capability ensures seamless collaboration among hardware and software teams, accelerating the development workflow while maintaining high-quality standards. More Details