Join Agnisys at DVCon US, where innovation and collaboration converge in the dynamic world of Design & Verification. From streamlined workflows to certified solutions, discover the tools that automate and accelerate your projects. Visit our booth #123 to delve into the forefront of design verification technology with Agnisys at DVCon US.

Accellera Workshops on IP-XACT and CDC

Join Agnisys and industry leaders at the forefront of design automation innovation during two highly anticipated Accellera Workshops at DVCon US 2025. These sessions offer a unique opportunity to gain invaluable insights into emerging industry standards, practical applications, and advanced methodologies that are shaping the future of semiconductor design and verification.

IP-XACT Workshop

Title: SoC development automation using IP-XACT 1685-2022 standard

Date: February 27, 2025

Time: 9:00 AM -10:30 AM 

Location: Siskiyou

CDC Workshop

Title: CDC/RDC Interchange Format Standard

Date: February 27, 2025

Time: 11:00 AM -12:30 PM

Location: Siskiyou

How Agnisys Powers AI Chip Innovation

• Automated Register Programming: Our IDesignSpec Suite simplifies CSR generation, ensuring seamless AI engine control.
• Rapid Architecture Exploration: With IDS-Integrate, designers can easily modify and interconnect IP blocks for optimized AI chip performance.
• Flexible Hardware Interface Generation: IDS-IPGen automates the creation of AMBA, TileLink, and CXL interfaces, crucial for AI chip communication.
• Built-in Safety Mechanisms: AI chips for autonomous vehicles and robotics must meet stringent standards like ISO 26262. Agnisys ensures compliance with auto-generated safety mechanisms.
• Clock-Domain-Crossing (CDC) Logic Generation: AI chips operate with multiple clocks. Our solutions automate CDC logic, enhancing reliability.