Introduction

IP-XACT stands for Intellectual Property exchange-Advanced Configuration and Integration of IP components. It is an IEEE standard (IEEE 1685) that provides a standardized format for describing and packaging electronic design intellectual property (IP). Think of it as a universal language for communicating the characteristics, configurations, and connections of various IP components within a design.

IP-XACT streamlines the process of IP packaging and integration by providing a common framework for describing IP components. It enhances interoperability between different design tools, allowing for seamless exchange of design data across the entire design flow. With IP-XACT, designers can easily create, package, and reuse IP components, leading to improved productivity and reduced time-to-market.

Key Concepts of IP-XACT

Component

A fundamental building block of IP-XACT, representing a functional unit or module within a design. At the core of IP-XACT is the concept of component-based design. IP-XACT allows designers to encapsulate IP components as reusable modules, each described using a standardized XML schema. These components can range from simple building blocks like registers and counters to complex processor cores and communication interfaces. By adopting a component-based design approach, designers can improve design reuse, modularity, and scalability, leading to more efficient and maintainable designs.

The IP-XACT schema for a component begins with the definition of the IP component itself. This includes attributes such as the component’s vendor, library, name, version, and description. The VLNV uniquely identifies a component. It may consist of one or more bus interfaces used for connections during integration. It may also contain registers organized inside one or more memory maps. Additionally, it may include parameters that define configurable aspects of the component, such as clock frequencies, data widths, and operational modes.

Bus Interface

IP-XACT facilitates communication between IP components through bus interfaces and memory maps. Designers can specify the interface characteristics, including ports, signals, protocols, and timing constraints, using IP-XACT. This standardized approach to interface definition promotes interoperability and compatibility across different IP components and design environments.

For an IP design with multiple bus interfaces, the schema defines each interface’s characteristics, including ports, signals, protocols, and timing constraints. Each bus interface may be described in detail, specifying its name, direction (input/output), protocol, address range, and associated signals.

Memory Maps:

The memory map section of the schema specifies the memory address space of the IP component facilitating memory-mapped communication between components within a design. It defines memory regions, address ranges, and associated attributes such as access permissions (read/write) and data widths. The memory map may include registers, memory blocks, and other memory-mapped peripherals within the IP component.

Configuration Parameters:

One of the key strengths of IP-XACT is its support for configurable parameters. Designers can define a set of parameters for each IP component, specifying characteristics such as clock frequencies, data widths, operational modes, and interface protocols. These parameters can be customized during instantiation, allowing designers to tailor the behavior of IP components to meet specific design requirements without modifying the underlying IP description. This configurability enhances design flexibility and promotes reuse of IP components across different design contexts.

Example IP-XACT Schema (ver 2022):

This example is taken from Accellera examples for illustration purposes.

<?xml version="1.0" encoding="UTF-8"?>

<ipxact:component 

xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"

      xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2022"

xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2022

http://www.accellera.org/XMLSchema/IPXACT/1685-2022/index.xsd">

   <ipxact:vendor>spiritconsortium.org</ipxact:vendor>

   <ipxact:library>Leon2RTL</ipxact:library>

   <ipxact:name>leon2Proc</ipxact:name>

   <ipxact:version>1.2</ipxact:version>

   <ipxact:busInterfaces>

      <ipxact:busInterface>

         <ipxact:name>AHBtarget</ipxact:name>

         <ipxact:busType

library="AMBA2"

name="AHB"

vendor="amba.com"

version="r2p0_6"/>

         <ipxact:abstractionTypes>

            <ipxact:abstractionType>

               <ipxact:abstractionRef library="AMBA2"

                                      name="AHB_rtl"

                                      vendor="amba.com"

                                      version="r2p0_6"/>

               <ipxact:portMaps>

               </ipxact:portMaps>

            </ipxact:abstractionType>

         </ipxact:abstractionTypes>

         <ipxact:target>

            <ipxact:memoryMapRef memoryMapRef="AHBtarget"/>

         </ipxact:target>

         <ipxact:connectionRequired>true</ipxact:connectionRequired>

      </ipxact:busInterface>

   </ipxact:busInterfaces>

   <ipxact:memoryMaps>

      <ipxact:memoryMap>

         <ipxact:name>AHBtarget</ipxact:name>

         <ipxact:addressBlock>

            <ipxact:name>AHBlowest1k</ipxact:name>

            <ipxact:baseAddress>0</ipxact:baseAddress>

            <ipxact:range>1 * (2 ** 10)</ipxact:range>

            <ipxact:width>32</ipxact:width>

            <ipxact:usage>memory</ipxact:usage>

            <ipxact:accessPolicies>

               <ipxact:accessPolicy>

                  <ipxact:access>read-write</ipxact:access>

               </ipxact:accessPolicy>

            </ipxact:accessPolicies>

         </ipxact:addressBlock>

      </ipxact:memoryMap>

   </ipxact:memoryMaps>

</ipxact:component>

Now that you know how to create a Component – the basic building block of IP-XACT. Next, we move onto a design that is a collection and connection of these IP components.

We will discuss that in the next article in this series. So stay tuned.