AI-Based Sequence Detection for IP and SoC Verification & Validation
A couple of years back at the Design Automation Conference (DAC), as I strolled through the exhibit floor, I couldn’t help but chuckle at how numerous Electronic Design Automation (EDA) vendors hopped onto the artificial intelligence (AI) and machine learning (ML) bandwagon. Many company slogans, booth posters, and demos boasted about the integration of AI/ML techniques into their products. While undoubtedly some of these claims were genuine, in certain cases, it was quite a challenge to believe them. In this post, I’ll delve into a tangible application of AI/ML technology at Agnisys that’s already up and running.
Let’s kick things off by clarifying some key terms. AI, which stands for Artificial Intelligence, serves as a broad umbrella encompassing computer programs that autonomously perform tasks that typically require human intelligence. AI excels when it amalgamates substantial datasets with rapid, iterative processing and clever algorithms. ML, or Machine Learning, operates within the AI realm, employing sophisticated techniques and models to enable computers to discern fascinating patterns within datasets and deliver practical AI solutions. In the realm of AI/ML, the bedrock of success lies in the quality and quantity of data used to train these models.
In the field of Electronic Design Automation, AI has ushered in a new era. This article will explore the AI advancements in SOC Verification, PSS, IP-XACT, SystemRDL, and UVM, bringing cutting-edge technology to the forefront.
In the realm of technology, one of the classic domains where advanced AI plays a pivotal role is Natural Language Processing (NLP). This field encompasses a fascinating array of applications, including machine translation, speech recognition, the development of conversational chatbots, and even the fine-grained analysis of language through Part-of-Speech (POS) tagging. NLP’s versatility extends to the development of Deep Learning (DL) models, which excel in tasks like text classification, translation, and more. Deep Learning, or DL, stands as a subfield of Machine Learning (ML) that draws inspiration from the intricate workings of the human brain. These techniques have consistently demonstrated their utility in tackling complex challenges in the NLP domain.
In the context of Electronic Design Automation (EDA), NLP becomes highly relevant. EDA involves the intricate process of designing and verifying IPs and chips. Interestingly, natural language remains the predominant format for specifying these designs. While there are established academic methods for translating these specifications into executable formats, NLP offers a promising frontier. Users often prefer the simplicity of describing their designs and features in plain English. In this regard, AI, ML, DL, and NLP have been instrumental in automating the conversion of these natural language specifications into executable formats.
This synergy between NLP and EDA proves particularly advantageous for tasks like PSS, IP-XACT, SystemRDL, and UVM IP in SOC Verification and Testing. It aligns with standards like the IP-XACT standard and SystemRDL 2.0, advancing the efficiency and accuracy of SoC validation and IP SoC verification. These technologies bridge the gap between technical specifications and practical implementation, enhancing the capabilities of SOC verification and testing tools. The future of EDA holds exciting possibilities as NLP and AI-driven techniques continue to transform the landscape.
At Agnisys, we’ve harnessed the power of AI to tackle an intricate challenge—processing sequence descriptions expressed in plain, natural language. Sequences are essentially ordered lists of steps, akin to flowcharts or algorithms, and they represent a fundamental aspect of any design specification. They play crucial roles in processes such as verification (utilizing SystemVerilog/UVM) and also come into play in areas like embedded code, IP/chip configuration, and backend testing and validation (in languages like C/C++). Sequences orchestrate a symphony of tasks, including reading and writing to registers and fields, manipulating the design’s pins, waiting for specific events, and calling functions and subsequences.
Our technology’s secret sauce lies in ‘auto-sequence detection.’ In essence, this involves our AI algorithms meticulously dissecting sequences articulated in natural language and converting them into executable formats, including SystemVerilog/UVM and C/C++. This isn’t magic; we methodically process each word one at a time, steadily generating the output information. What sets us apart is our use of a bidirectional layer—a smart approach where we analyze the input text from both forward and backward directions. This clever maneuver significantly enhances our model’s ability to classify sequences. Our algorithms are fine-tuned to predict the most likely expected output sequences based on the text specifications.
Our work at Agnisys isn’t just about advancing sequences; it’s about enhancing the efficacy of PSS, IP-XACT, SystemRDL, and UVM IP in the realm of SoC verification and testing and SoC validation. We’re bridging the gap between natural language specifications and technical implementation, and this technological synergy has the potential to revolutionize how we approach IP soc verification. The future of Electronic Design Automation holds great promise as the SystemRDL compiler and IP-XACT standard find more effective utilization in SOC verification and beyond.
In any AI/ML application, the data that is fed to the model for training should be as good as possible. The dataset (corpus) must be appropriate to produce better performance from the model. We have carefully created our corpus by obtaining actual register programming sequences from industry and introducing a wide variety of cases including cases with augmented data and noise. This has yielded a robust model with high accuracy, covering almost all scenarios of sequences that can be described in a text specification.
We have auto-sequence detection available now in our recently announced IDS NextGen™ (IDS-NG) solution. It could not be more accessible for users to:
- Create their IP specification
- Click the “Check” button to detect any specification errors
- Select the sequence template and specify sequences in natural language (English)
- Review the sequence steps interpreted by NLP
- Select the desired output files
- Click on the “Generate” button to produce the outputs using those sequence steps
The following table shows just a few examples of natural language sequence descriptions and the sequence steps generated by NLP.
We’re elated by the outcomes yielded by our present solution, which we’ve extensively deployed across a diverse array of real-world test scenarios. The results have been nothing short of outstanding, achieving an accuracy rate exceeding 90%, all while maintaining a seamless flow in the inference process. Our model showcases a remarkable knack for effectively managing noise in the input text, diligently focusing on the salient segments that exert a profound influence on the generation of precise output sequences.
What distinguishes our approach is its impressive scalability, effortlessly spanning from individual PSS and IP-XACT to SystemRDL and SystemRDL compiler, encompassing IP-XACT standard, SystemRDL 2.0, and SoC verification and testing. We’re also proud to handle soc validation and IP soc verification, expertly navigating through UVM SoC and ensuring the integration of UVM IP configurations. For those grappling with substantial designs, we offer invaluable cloud support through IDS-NG, granting access to expansive computing resources.
At the heart of our ethos is an unwavering commitment to perpetual enhancement—a principle that holds particular significance in the realm of Natural Language Processing (NLP). It’s a defining characteristic of AI in its broader scope and more specifically, Machine Learning (ML) and Deep Learning (DL). The truth is, applications in this sphere are never truly ‘complete.’ Learning is an ongoing journey, and our training dataset steadily expands, culminating in heightened precision and resilience. As we press forward, we aim to broaden our vocabulary recognition, handle unknown terminology with even greater finesse, offer more effective guidance when textual specifications are scant, and navigate the complexities of hierarchical and intricate sequence scenarios.
The legacy of Agnisys has been deeply intertwined with the realm of design and verification automation, spanning the gamut from registers and sequences to testbenches, embedded code, and the orchestration of System-on-Chip (SoC) assemblies. With our groundbreaking ‘auto-sequence detection,’ we’ve taken a momentous stride in empowering users to articulate their verification and validation sequences in plain language, while simultaneously and autonomously generating output formats. This transformative leap not only translates into substantial time savings in UVM and C/C++ coding, both at the outset and as designs and sequences evolve but also ensures a uniform understanding of sequences across project teams. For a deeper dive, we invite you to explore our recent ebook.
