Taking Stock of the Past Year
As we transition into 2023, it’s a good time to look back over the past year and assess it, much as I did a year ago. Of course, every year has high and low points, but I have to say that 2022 was positive for Agnisys. For one thing, in-person industry conventions returned in force, some for the first time in several years. The biggest event, as usual, was the Design Automation Conference (DAC) in San Francisco. It was back in a traditional summer slot and was quite well attended.
DAC is always fun since we get to see many old friends and meet with customers. Especially with curtailed business travel in recent times, we haven’t had much face-to-face interaction. Video conferences are very helpful, but they’re not a true substitute for meeting in person. It’s also nice to be able to demonstrate our latest tools and technology live, in the interactive setting of a trade show booth, with our experts on hand to answer your questions.
This year at DAC, we highlighted our emerging “Complete IP” solution. We’ve been automating the generation of RTL code for registers and memories for many years, and over time have added automation of simulation testbenches and tests, assertions for formal verification, IP integration and hookup at the full-chip level, C/C++ sequences, and user documentation. We generate all this automatically from your specifications, and we’ve now added support for more aspects of design.
You can now specify finite state machines (FSMs), datapaths, signals, and other parts of your IP design in executable format. We generate the RTL code for these elements today, and we are adding more capabilities all the time. My vision is that you will be able to completely describe your custom design blocks in executable specification format, configure all the standard IP blocks you want, and interconnect all the blocks by a chip integration specification with no hand-written RTL at all.
We attended more events in 2022 than just DAC. We were delighted to host a booth at the in-person Design and Verification Conference (DVCon) in India once again. Although DVCon in the U.S. was still virtual, we participated very actively. We offered the short workshop “IP/SoC Design, Co-Verify, Co-Validate, Co-Everything in 90 minutes!” and presented the paper “Automatic Translation of Natural Language to SystemVerilog Assertions” in the technical track.
This DVCon paper provided some of the details on our iSpec.ai technology, which we introduced last year. As users provide increasingly detailed English natural language statements of design intent, this technology persistently advances. We have incorporated the capability to translate English sequence descriptions into executable formats for generating sequences in SystemVerilog and C/C++. As we have done over the last few years, we offered a webinar series that covered a wide range of technical topics. We provide background on a key challenge facing design or verification engineers and then demonstrate how our solutions can help. Topics included automated SoC assembly, system-level validation of RISC-V processors, highly configurable IP generators, and generation of portable sequences. Recordings of all webinars are available on demand.
Finally, I’d like to remind you of our biggest announcement of the past year, and one of the accomplishments of which I am most proud. The international test agency TÜV SÜD certified that the Agnisys IDesignSpec Suite of products and our development flow have achieved the stringent tool qualification criteria defined by ISO 26262 for automobiles and other road vehicles as well as the related underlying functional safety standard IEC 61508.
This means that you can use our products in your IP or SoC development flow without having to do any work at all to assess compliance with these important standards. TÜV SÜD conducted a detailed months-long investigation of our tools, our team, and processes. This included audits of our product verification and validation flow, quality assurance (QA) procedures, configuration and release management, and even the ways that we support our users. I am proud that we passed the test.
I am also proud of all that the Agnisys team has accomplished over the last twelve months. In the hectic and high-pressure world of high tech, we sometimes forget to take a step back and realize how far we’ve come. I hope that you can look back on 2022 with similar pride and satisfaction while knowing that there’s another busy year already looming. I wish you a healthy and happy holiday season and all the best in 2023.
There are multiple causes for designs being wrong, but some of the most common are related to the design specifications and how they are distributed and maintained throughout the product development lifecycle. Learn how to address this issue by reading The IC Designer’s Guide to Automated Specification of Design and Verification, for Better Products.
