A Unified Flow for Embedded Systems Development
Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual Design Automation Conference (DAC). We’re expanding from automating register design and verification to covering various facets of embedded systems development, building on our expertise. We provide real value to your architects, designers, verifbication engineers, software developers, technical writers, and chip testers.
The key idea that links all our products and solutions is using an executable specification as the single source of information across all your project teams. From a single specification, you can generate design RTL, complex programming and test sequences, UVM testbench models for simulation, portable stimulus standard (PSS) models, assertions for formal verification, C code for firmware and device driver development, CSV files for automatic test equipment (ATE), and end-user documentation in multiple formats. Avoiding information duplication prevents waste of time, money, and resources and maintains accuracy as the project progresses. Changes to the specification require only the push of a button to update all generated files. We support a wide range of specification formats, including industry standards such as IP-XACT and SystemRDL, popular tools such as Microsoft Word and Excel, and our specialized editors. We generate output files in dozens of different formats to support the diverse users in your teams.
We first implemented this approach for control and status registers (CSRs) and over the last few years, we have extended it in several directions. As a quick summary, here is the range of our current products:
- IDesignSpec™ (IDS) automates the design, verification, and documentation of your CSRs
- IDS-Verify™ generates a comprehensive UVM testbench and test sequences
- IDS-Validate™ generates device driver building blocks and supports bare-metal verification
- IDS-Integrate™ assembles a complete SoC from IP and your design blocks
- IDS-IPGen™ is a set of configurable IP generators
We have come a long way from being a single-product company focused solely on register design. This year’s products fulfill our vision of a fully automated solution, covering registers and sequences from specification to validation. But it takes more than products to provide a complete solution; a methodology-based flow is also needed. We have worked with our leading users to develop and validate such a flow and will be presenting it in an upcoming webinar.
We invite you to join us for “System Development Using Agnisys: The Fastest Path to an Embedded System from Specification” to fill in all the details. This event is being held at the following times:
- 30 October, 10:00 AM-11:00 AM KST (Korea)
- 29 October, 6:00 PM-7:00 PM PST (USA)
- 30 October, 06:30 AM-07:30 AM IST (India)
If this time is not convenient for your location, note that a recorded version of the webinar will be available for later viewing. You can learn more and sign up here. I hope you can join us to witness the value we offer for your intricate SoC-based embedded systems projects.
