Agnisys Presents Implementation-Level Sequence Generator at CDNLive
San Jose, California – March 20, 2019 – Agnisys Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of the Hardware/Software Interface (HSI), has been invited to present at CDNLive Silicon Valley to be held on April 2-3, 2019 at Santa Clara, CA.
Session Track: SoC / System Verification
Perspec™ System Verifier and ISequenceSpec™, Enabling Spec to Validation Portability
Speaker: Neena Chandawale, Application Engineer, Agnisys
Tuesday, April 2nd | 2:15pm – 2:55pm | Room 207
The goal of Portable Test and Stimulus Standard (PSS) is to enable SoC teams to specify stimulus and tests at a high-level of abstraction. This avoids implementation-level detail of the tests such as register reads/writes and pin manipulation commands. Users create the implementation-level sequences in some way and “stitch” them with the output generated by the PSS processing tool. Users create the test intent using PSS and generate C/UVM/SystemVerilog sequences from it, however, the HSI layer is not part of this description.
“Our solution provides the full interface layer for the registers, memories, interrupts, and pins,” said Anupam Bakshi, Agnisys Founder, and CEO. “ISequenceSpec now supports Perspec System Verifier. Users are now able to write sequences from a golden specification (spreadsheet or txt format) and auto-generate the C/UVM/SystemVerilog sequences with the corresponding PSS ‘exec’ blocks.”
See Technical Demonstrations of Agnisys HSI solutions at CDNLive Booth:
- IDesignSpec™ – An end-to-end solution for centralizing register design and verification from a golden specification in Word, Excel, IP-XACT or SystemRDL. Auto-generates sign-off quality register RTL code, UVM models, C/C++ headers and HTML/PDF documentation.
- ISequenceSpec™ – An add-on to IDesignSpec where users can define sequences from a single specification and auto-generates portable UVM/C/CSV sequences for simulation, firmware, and post-silicon validation. Includes interface with PSS tools for auto-generating UVM/C sequences within ‘exec’ blocks.
- ARV™ – An add-on to IDesignSpec that auto-generates a complete UVM environment with sequences for RTL simulation and assertions for formal verification, providing 100% functional coverage.
About Agnisys
Agnisys, Inc. is a leading supplier of Electronic Design Automation (EDA) software for solving complex design and verification problems for system development. Its products provide a common specification-driven development flow to describe registers and sequences for System-on-Chip (SoC) and intellectual property (IP) enabling faster design, verification, firmware, and validation. Based on patented technology and intuitive user interfaces, its products increase productivity and efficiency while eliminating system design and verification errors. Founded in 2007, Agnisys is based in Boston, Massachusetts with R&D centers in the United States and India.
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Learn how Agnisys approaches a solution to this challenge that is available today.
