DVCON 2014: Strong Focus on both, Design & Verification

Here we go! The Design and Verification Conference (DVCON 2014) is round the corner. Make sure you register for the event which has been one of the premier conferences for IC design and verification engineers. This year’s event looks even bigger with better focus on both, design and verification.

A look at the agenda of lined-up keynote sessions, topics of panel discussions and tutorials gives an impression that the focus this time continues to be on verification while effort of reaching out to the design engineers is evident in the agenda with increasing content about front-end design accommodated very well.

The topics included in the panel discussions and tutorials cover the specifics of design & verification on various levels of system design, interoperability of IP/tools, advanced methodologies and test-benches, debug techniques, optimization of coverage-driven verification, etc. which calls for an engaging show for one and all of us.

We are excited about the event because this is the time we get to see our customers and potential customers. Our engineering team has been exuding a lot of energy because of a new development underway – code named: ‘Mystic Tool’ with almost super natural capabilities to help engineers write their code better!

Needless to say, we are very excited about giving you a sneak peek at the technology behind this magic.

We are going to show the latest in the Executable spec creation arena, where we find ourselves as the single contender to the coveted leadership position. We will show off the new features recently included into our flagship product IDesignSpec™ such as: Interrupts, Multiple Bus Domains, Automatic Register Verification and Special Registers.

We welcome you to the Agnisys booth #302. You can click here to register with us and see us for the demonstrations and presentations well in advance, allowing us to schedule some quality time together.

The readers can rest assured that the demonstration of IDesignSpec™ and ‘Mystic Tool’ at DVCon will leave all your design & verification needs addressed.

While emphasis this year at DVCON is on the Design part and the effort is being put to balance out the focus on Design and that on Verification as well in the show, it can be certainly said that every design and verification engineer will find something of interest in DVCON 2014.

Here is a list of events at DVCON 2014, followed by a brief on Agnisys activities. For further information about Agnisys activities at DVCON 2014, click here.

And don’t forget to register with DVCON 2014 at DVCON website to see us at Agnisys booth #302!

DVCON 2014 is going to be biggest in terms of number of attendees?

Here is our recommended list of presentations at DVCON 2014 for you …

MONDAY MARCH 3

(Exhibit hours 5:00pm – 7:00pm)

Tutorial 1: UVM – What’s Now and What’s Next (9:00am – 12:00pm)

TUESDAY MARCH 4

(Exhibit hours 2:30pm – 6:00 pm)

Session 1: System-Level Design – 1 (9:00am -10:30am)

Session 3: HW/SW Co-Verification (9:00am – 10:30am)

Poster Session (10:30am – 12:00pm)

Sponsored Luncheon: System to Silicon Verification – Challenges & Solutions (12:00pm – 1:15pm), Cadence

WEDNESDAY MARCH 5

(Exhibit hours 2:30pm – 6:00 pm)

Session 8: Advanced Stimulus Generation (10:00am – 11:30am)

Session 9: Advance Methodologies and Test benches – II (10:00am – 11:30am)

Sponsored Luncheon: Accelerating Verification (12:00pm – 1:15pm) Mentor Graphics

Panel: Did We Create the Verification Gap? (1:30pm – 3:00pm)

AGNISYS AT DVCON 2014

Presentations and Talks at Agnisys Booth #302

– Agnisys in DVCON Booth Crawl Session– Monday, March 3, 5pm-7pm

• Kick-off the talks in a relaxed environment

– IDesignSpec

• New Capabilities and Advanced Features

New Features	Advanced Features
Special registers Shadow Shared Aliased Modal Lock Automatic Datasheet Automatic Register Verification	Parameterization Interrupts Tcl API Low Power RTL Same address registers Multi Dimensional Registers All types of access MISRA C output Multiple Bus Domains