SOC DESIGN

SoC Design

Developing a modern system-on-chip (SoC) device is challenging in many ways, but it starts with the design. Without a design, there’s nothing to verify, program, or validate. The design begins as a register-transfer-level (RTL) description, is transformed into gates and transistors by logic synthesis and layout tools, and is ultimately fabricated in silicon.

IT all Starts with IP

Even a team with hundreds or thousands of designers cannot design today’s huge and complex SoCs from scratch. Even if such an approach was possible, it would be way too expensive and could not meet tight time-to-market (TTM) requirements. A contemporary SoC might have 90% or more of its RTL blocks reused from previous projects or licensed from intellectual property (IP) providers.
Commercial IP allows RTL designers to focus their efforts on the parts of the SoC that offer product differentiation rather than reinventing the wheel for common design blocks. However, a “one size fits all” approach for IP is too limiting. Many standards have choices such as data width, optional features, and provision for custom extensions.
The upshot is that IP must be configurable and customizable. This provides all the desired benefits in terms of schedule and cost savings while not limiting the end functionality and potential markets for chips. Designers have to be able to scale design parameters, select applicable options, and add their own teaks to the IP without manual editing.

IDS-IPGen: Configurable & Customizable IP Generation

Agnisys simplifies SoC IP generation with IDS-IPGen™, part of the IDesignSpec™ Suite, enabling designers to create custom and configurable RTL IP blocks. This generative approach allows easy customization to meet specific application needs.

With IDS-IPGen, designers can tailor key attributes like bus widths, port numbers, and optional functionalities using an intuitive graphical interface. If requirements change, simply re-generate the IP with updated specifications.

Many IDS-IPGen-generated functions comply with industry standards, reducing the need for in-depth expertise. Supported IPs include AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPI, Timer, and UART.

Support for Custom IP & Unique Designs

While commercial IP blocks form the foundation of many SoCs, differentiation comes from custom IP. IDS-IPGen streamlines custom finite state machine (FSM) generation, while IDesignSpec GDI and IDS-Batch CLI handle registers and memories—all in synthesizable RTL for simulation and synthesis.

Since SoCs require both hardware and software, the IDesignSpec Suite also generates UVM sequences for verification and C/C++ code for validation and software development, ensuring seamless integration across the entire design flow.

Hooking up IP Blocks Is a Pain

SoCs contain hundreds or thousands of design blocks, most of them replicated many times. In the final stages of RTL design, all these blocks must be connected together at the full-chip level. Manual hookup is tedious, time consuming, and subject to errors. A chip with 400 block instances, each with an average of 100 ports, requires 40,000 connections to be made.
Signals may run from leaf-level blocks up to the top level and then back down to other leaf blocks, with dozens of connections and renames along the way. Similar signal names exacerbate the problem. Multiple instantiations of blocks generally connect to signal names that differ only in prefixes or suffixes. It’s impossible to keep all of this in mind when typing in connections by hand. 
Just as with the specifications for IP blocks and registers, top-level hookup specifications change many times over the course of projects as designs and requirements evolve. The ripple effects of changing just a few blocks can be significant when scaled over many instantiations in large SoCs. Manual RTL editing is no longer an acceptable approach.

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IDS-Integrate: Automating IP Integration for SoC Design

IDS-Integrate™ simplifies and automates the integration of IP blocks into a complete SoC. It efficiently stitches IPs using buses, interfaces, or wires, ensuring seamless connectivity across the design.

Key Capabilities

  • Automated IP Hookup: Connects IPs using predefined rules, reducing manual effort.
  • Intelligent Name Mapping: Matches ports with identical or similar names for hassle-free integration.
  • Bus & Interface Handling: Automatically generates aggregators, bridges (AHB to APB, AXI to APB), and multiplexers as needed.
  • Hierarchy Management: Restructure, flatten, or partition the design for optimal organization.
  • Multi-Format Support: Works with IP-XACT, SystemRDL, RTL, and third-party IPs.
  • Scripting & API Integration: Define connections using Tcl, Python, Java, or C++ APIs.

With IDS-Integrate, designers can assemble a complete SoC faster, with fewer errors, while ensuring a well-structured and scalable architecture.

Agnisys Automates SoC Design

To meet ever tighter TTM requirements for ever larger and more complex SoCs, designers can no longer write and interconnect all their RTL blocks by hand. Agnisys provides specification automation solutions that generate correct-by-construction RTL designs plus files to help with verification, validation, and software. The benefits of this automation are replicated every time that specifications change. The result is faster chip development with fewer resources and increased confidence.

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