DAC 2026
Agnisys is the Pioneer and Industry Leader in Golden Executable Specification Solutions™
Meet us at Booth #1557 at DAC 2026 and discover how we automate the entire path from specification to silicon.
Schedule a meeting with our experts by completing the form on the right!
July 27-29, 2026
Long Beach, CA
We are excited to exhibit at DAC 2026, where innovation and collaboration drive the future of chip design and verification. Discover how Agnisys empowers teams with streamlined workflows, certified solutions, and intelligent automation to accelerate development. Visit us at Booth #1557 to explore our advanced design and verification technologies.
Engineering Presentation
We will present an innovative DFT automation methodology that integrates Design-Aware Test Points (DATP) directly into the SystemRDL-to-RTL generation flow. This approach addresses TCPF hotspots at the source, enabling significant ATPG pattern reduction and improved test efficiency for complex system-on-chip (SoC) designs, with up to 4× TCPF improvement and 50% reduction in top-level ATPG patterns with minimal area overhead.
Presenters: Veerabhadrarao Vasa & Rajesh Gottumukkala from Google and Freddy Nunez from Agnisys
Date & time: Tuesday, July 28 / 11:15 – 11:30 AM PDT
Venue: Seaside RM 7
Explore live demonstrations of IDS-AI™ & IDS-NoC™ and discover how Agnisys is accelerating chip development from golden specification to sign-off through intelligent automation and Agentic AI.
IDS-AI™: From Specification to Sign-Off, Dramatically Faster
Agnisys will showcase IDS-AI, the industry’s first agentic AI framework purpose-built for semiconductor development. With nearly 45% of functional bugs originating from incorrect or incomplete specifications and only 14% of ASIC projects achieving first-silicon success, IDS-AI addresses issues where they begin at the specification stage. Instead of relying on disconnected tools and manual handoffs, IDS-AI spans the entire development flow, understanding design intent and driving specification creation, RTL generation, integration, and verification within a unified framework. It automatically delivers complete CSR verification coverage, identifies costly issues before implementation starts, and significantly reduces manual effort from golden specification to sign-off by combining advanced AI reasoning with the correct-by-construction methodology Agnisys has perfected over more than two decades.
IDS-NoC™: Scalable Network-on-Chip Automation
Agnisys will also showcase IDS-NoC, a solution designed to remove one of the most challenging bottlenecks in modern SoC development creating an interconnect fabric that can scale for AI accelerators, automotive systems, and multi-core processors without encountering the timing and integration limitations of traditional crossbar architectures. Rather than manually designing routers and network interfaces, engineering teams can automatically generate a complete, deadlock-free NoC fabric with unlimited scalability across instances and interconnect blocks. Since the generated RTL is delivered as an open, plain-text SystemVerilog instead of a black-box implementation, teams maintain complete visibility and control over their IP. The result is reduced integration effort, accelerated time-to-market, and an interconnect architecture ready to support increasingly complex designs.
Market Segments:
Agnisys serves a wide array of market segments including:
- Artificial Intelligence (AI)
- Automotive
- Autonomous Technology
- Cloud-Edge Computing
- Information & Technology
- Intellectual Property (IP)
- Military/Aerospace
- Mobile/5G
- Research and Science/Engineering Services
- RISC-V
- Semiconductors
