Agnisys: The AI Chip Enabler

 

As AI seems to be taking over the world, and AI chips seem to be taking over the semiconductor industry, we at Agnisys are finding that we have a great solution to help foster this revolution. As I mentioned in a recent blog post, AI within our own tools is one aspect of that solution. In this post, I’d like to explore in more detail how our IDesignSpec™ Suite enables you to develop large, complex chips designed for AI applications.

Anatomy of an AI Chip

At first glance, developing an AI chip might not seem very different from designing an advanced central processing unit (CPU) or network switch. However, the types of algorithms used by AI applications are quite different from traditional methods. Classic programming relies on an explicit sequence of steps: the software engineer tells the hardware what to do, and it does what’s requested. We might call this prescriptive programming in that the programmers are making all the key decisions.

AI is much more adaptive than prescriptive. True, there is still user-written code at its core, but it executes in ways that the programmer could not have anticipated. Machine learning (ML) and deep learning (DL) techniques constantly absorb new information and adapt the computations to this changing knowledge base. This produces unexpected results and new ways to solve problems so innovative that some observers claim AI agents exhibit creativity and human-like thought.

Designing a chip to do this type of computation requires massive parallelism, especially for multiply-accumulate functions. Graphics processing units (GPUs) provide such parallelism and have been widely used for AI. Other options are emerging, such as hardware transformers for natural language processing (NLP), language translation, computer vision, audio processing, and similar applications. AI chips also require massive amounts of fast memory, high-speed communication channels, and often real-time access to data from sensors.

Flexibility is the Key

AI algorithms have great power, but they can lead to hallucinations and other undesirable results if left unchecked. AI model layers, weights, operations, and functions provide the necessary level of control to guide the computation for best results. However, this is a challenge in AI chip design since all these parameters are too variable to be implemented directly in fixed hardware. Core AI engine design entails providing sufficient flexibility.

The best way to provide this adaptability is with an array of status and control registers (CSRs) that program the AI engine with weights, parameters, hyperparameters, etc. Weights control the connections between neurons in artificial neural networks (ANNs). This influences how data flows through the network and affects the accuracy of results. CSRs provide a convenient way to initialize and configure the weight values, adjusting them as needed to adapt to the data being processed.

Hyperparameters are important in ML because they configure the way that the AI model learns, for example the size of an ANN. Models may not produce useful results if the correct hyperparameters are not chosen, but it can take time to tune the hyperparameters,* so they must be flexible. As with weights, CSRs offer you an easy way to configure hyperparameters to train a model, test its operation, and produce the best results with high performance. 

The Agnisys Way for AI

Agnisys is the industry’s pioneer in specification automation, starting with CSRs. For years now, we’ve been generating design, verification, software, validation, and documentation files for complex register maps from executable golden specifications. Our IDesignSpec Suite accepts many input formats, including IP-XACT and SystemRDL. We support special CSR types such as indirect, indexed, read-only/write-only, alias, lock, shadow, interrupt, paged, virtual, external, read/write pairs, and many possible combinations. You have all the power you need to control your flexible AI chip.

In addition to registers, other elements common to all AI chips are state machines and buses. Our IDS-IPGen™ solution allows you to develop many parts of your IP blocks within your design, including state machines, from executable specifications. We also generate hardware bus interfaces for your IP, including the widely used AMBA, TileLink, and CXL protocols. The standard IP blocks generated by IDS-IPGen also include these bus interfaces if you so desire.

Another requirement for AI chip development is the ability to rapidly explore different architectures to see which produces the best results. We provide IDS-Integrate™ to automatically connect both standard and custom IP blocks at the full-chip level from a simple executable specification. If you want to try a new approach, you don’t have to toss most of your RTL code and start over. You simply update your specification and re-generate the top level of your design.

We do more than just interconnect your blocks. We generate bus multiplexors, aggregators, and bridges wherever needed. We generate clock-domain-crossing (CDC) logic as well, important because AI chips always have multiple clocks. Many AI chips are used in safety-critical applications such as robotics and autonomous vehicles, and must follow safety standards such as ISO 26262. We also generate appropriate safety mechanisms to protect your design against potentially dangerous faults.

Come and See for Yourself

If you want to learn more about how Agnisys can help you design your next AI chip, I invite you to join us at DVCon U.S. in San Jose, California later this month. We’ll have a booth in the exhibit hall on February 25 from 1:30 PM until 5:00 PM and February 26 from 1:00 PM until 5:00 PM. Then, on February 27, we’ll be speaking at two Accellera workshops of great relevance for AI chips:

• IP-XACT Standard, from 9:00 AM until 10:30 AM
• CDC/RDC Interchange Format Standard, from 11:00 AM until 12:30 PM

I’ll close by saying that nothing in this post is theoretical or a future promise. We have customers today designing big, hairy AI chips. You can read all about one of them in a recent post. You can be just as successful with our IDesignSpec Suite. Please stop by our booth and learn how. Oh and we have a special gift for AI chip designers, please do stop by to ask for it!