Agnisys now supports Duolog format for IDesignSpec
The input format of Duolog is now supported by IDesignSpec with outputs including Verilog, UVM, CHeader, and SystemC. The outputs generated are compatible with both Duolog as well as IDesignSpec formats. We have incorporated multiple special enhancements and new features to support Duolog compatibility and making the output generation 10x faster.
Users can create and validate code from the specification itself and experience its benefits with faster RTL and more versatile UVM. We have created a drop-in replacement for several outputs like Verilog, Verilog header, SVheader, Cheader, UVM, etc. for a few of our Duolog users.
Out-of-the-box Features
- Implementation of advanced properties for our users. For instance; adding an additional map, same as default map in UVM for multiple bus domains, making UVM relocatable from one chip to another chip.
- Implementation of System level C-test as one of the outputs for faster and effective results.Duolog compatible system level C-test enables users to generate both UVM sequences and C-test simultaneously with the same specification in a fraction of seconds. Hence, tests as well as sequences, are well evaluated and validated.
- Another interesting feature which we have incorporated is “parity” for bus data and register data.
Benefits for our Users
- We now support Duolog’s “input excel document” and output format (-in_third_party d for taking Duolog input, and -out_third_party d for generating Duolog Verilog and UVM outputs).
- We have successfully matched the Duolog output, right from flattening of registers and regGroups to creating an external widget that will add a delay to the IP_READY signal for external registers in Verilog and generate extra code (set_compare, option.per_instance, set_check_on_read etc.) to make UVM relocatable in UVM output.
- For Verilog, we have a command line option that makes the bus port case sensitive (bus_port to UPPER/LOWER using “-bus_port_case upper/lower”). In addition, we have a command line to specify the default reset using “-default_reset async/sync”. We have the capability to limit the generation of read and write error that is generated in IDesignSpec by default using “-rtl_no_error”. We have created non-piped axi_widgets (AXI4Lite and AXI4Full with burst) which are not supported in Duolog format.
- For UVM, we have added code for UVM_CHECK (option.per_instance, set_check_on_read, set hdl_paths in uvm.configure to null, etc). We have changed the block class similar to Dulog format (“abc_block” to “abc_t”). We have created an additional property to generate multiple regmaps. We now support “vertical_reuse” property, that will make the UVM relocatable.
- In General, we have created a Duolog compatible SystemC output. User can create multiple PDF and svheader file for each block using command line option “-if_pdf” and “-if_svheader” respectively. We also support “-top_property” to specify any property at the top level module and “-mbdc” to mention the multiple, bus domain table on the command line for inputs that don’t support multiple bus domains in the register format, for example, IP-XACT.
