SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES
I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series...
Introduction With growing advancements in hardware designs, the complexity of designs has increased multiple folds and brought great challenges to...
Navigating SoC Complexity System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design...
While more registers mean more functionality and configurability, more is not always better...
Modern RTL design verification (DV) environments are both compelling and very complex. They include advanced simulation testbenches plus support for...
We talk about the creation of complex registers in IDesignSpec and the generation of their suitable RTL and UVM models...
Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and...
In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM)...
