SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

Our Latest Blogs

Addressing MAC and Linux GUI needs for Register & Memory Map Specs.

We all have different tastes and different habits and when it comes to work we like to work in different...

Specification Automation for Formal Verification

I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series...

Tool Qualification Kit for Functional Safety Compliance

Introduction With growing advancements in hardware designs, the complexity of designs has increased multiple folds and brought great challenges to...

Smart Assembly of SoC Designs

Navigating SoC Complexity System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design...

Making Way For Register Specification Software

While more registers mean more functionality and configurability, more is not always better...

Correct-By-Construction SystemVerilog UVM Testbenches

Modern RTL design verification (DV) environments are both compelling and very complex. They include advanced simulation testbenches plus support for...

How To Create Complex Registers in IDesignSpec

We talk about the creation of complex registers in IDesignSpec and the generation of their suitable RTL and UVM models...

Agnisys | Next Generation of Register, Sequence, and SoC Automation

Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and...
Scroll to Top