SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES
Modern RTL design verification (DV) environments are both compelling and very complex. They include advanced simulation testbenches plus support for...
We talk about the creation of complex registers in IDesignSpec and the generation of their suitable RTL and UVM models...
Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and...
In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM)...
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry...
Modern SoCs get more and more complicated every day. As the complexity of modern electronic semiconductor device design increases, niche...
Introduction As per the IP-XACT User Guide, IP-XACT defines an API called Tight Generator Interface (TGI) to query, modify, create...
By Louie De Luna, Agnisys Chief Product Evangelist...
Just about a year ago, I published a blog post about the emerging need for better functional safety and security...
