SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Specification-Driven UVM Testbench Generation

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM)...

Agnisys makes Design Verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry...

5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

Modern SoCs get more and more complicated every day.  As the complexity of modern electronic semiconductor device design increases, niche...

Tight Generator Interface support in SoC-E

Introduction As per the IP-XACT User Guide, IP-XACT defines an API called Tight Generator Interface (TGI) to query, modify, create...

An Update on Functional Safety and ISO 26262

Just about a year ago, I published a blog post about the emerging need for better functional safety and security...

Semiconductor Data Sheet Automation – Just The Way You Want It

Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of...

Next Gen SystemRDL: Implementing Registers with IDesignSpec

Typically thousands of registers are required for today’s complex designs, which are used to control the operations of the SOC...
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