SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Why is it difficult to make your first EDA tool sale?

As you know we have created a brand new EDA tool that saves people a lot of time and money...

Agnisys – Certified Safe for ISO 26262 Design

Agnisys has customers designing all sorts of intellectual property (IP) blocks, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and...

Tales from the DVCon 2016 – Portable Stimulus Resonated

The DVCon Conference this year, was quite eventful for us with a lots of visitors at our booth. We were...

Age of cooperation, is it?

Its heartening to see greater cooperation between various EDA companies, both big and small. The ongoing work under Accellera for...

Questa® VIP validates IDesignSpec generated IP

In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If...

DVCon 2014 wrap-up

  DVCon 2014 was a wrap. It was marked by record attendance and participation both by the DV Community and...

Great turnout at the Design Automation Conference

We had a great first day at DAC. All the talk about recession and economic doom were hard to believe...

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys...
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