SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Expanding the Scope of Specification Automation

Late last year, I published a blog post that summarized what had transpired for Agnisys over the course of 2021...

How safe is your ride?

The Intersection of Functional Safety and Electronic Design In an industry that has gone through an incredibly rapid transformation over...

Automatic Handling of Register Clock Domain Crossings

Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and...

Agnisys Commitment to Customer Success: A Competitive Advantage

The Agnisys IDesignSpec™ Suite offers development teams a closely linked set of products, including a unified graphical design interface (GDI)...

Different flows for UVM Register Generation

The UVM register model is an essential component of the UVM-based verification for modern designs. In this article, we discuss...

Power of SystemRDL to IP-XACT Conversion: Streamlining IP Integration

In the ever-evolving landscape of semiconductor and electronic design, the pursuit of efficiency, consistency, and reusability remains paramount. Designers frequently...

Bridging the Gap: Agnisys Contribution to Specification Automation

Agnisys offers a leading solution with comprehensive features to guarantee the accuracy of each semiconductor component right from the beginning...

Deep Dive into UVM Register Model

UVM Register Model, a key component of the Universal Verification Methodology (UVM), is a standardized methodology for verifying digital designs...

Streamlining Design Verification with UVM RAL for Efficient Register Access

In system design, engineers grapple with two formidable challenges: the relentless miniaturization of technology nodes and the ever-pressing demand for...
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