SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Different flows for UVM Register Generation

The UVM register model is an essential component of the UVM-based verification for modern designs. In this article, we discuss...

Power of SystemRDL to IP-XACT Conversion: Streamlining IP Integration

In the ever-evolving landscape of semiconductor and electronic design, the pursuit of efficiency, consistency, and reusability remains paramount. Designers frequently...

Bridging the Gap: Agnisys Contribution to Specification Automation

Agnisys offers a leading solution with comprehensive features to guarantee the accuracy of each semiconductor component right from the beginning...

Deep Dive into UVM Register Model

UVM Register Model, a key component of the Universal Verification Methodology (UVM), is a standardized methodology for verifying digital designs...

Streamlining Design Verification with UVM RAL for Efficient Register Access

In system design, engineers grapple with two formidable challenges: the relentless miniaturization of technology nodes and the ever-pressing demand for...

Agnisys: Pioneers in Specification Automation and Beyond

In the ever-accelerating landscape of technological advancement, Agnisys has emerged as a trailblazer, reshaping the electronic design automation (EDA) industry...

Custom IP Design and AI-Based Verification

Introduction Engineers have consistently strived to expedite ASIC development. Our latest endeavor at Agnisys introduces automation that captures specifications in...

Three Smart Steps to Quickly Test a Register Map for Your Entire SoC

As I noted in a recent post, registers appear everywhere in system-on-chip (SoC) design. Architecturally defined registers form the hardware-software...

Unlocking Efficiency in Semiconductor Design with the PSS Compiler by Agnisys

In the world of semiconductor design, where precision and efficiency are of utmost importance, the demand for streamlined methodologies is...
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