SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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2015 Year End review – DV Challenges

Wow, what a marvelous year 2015 has been to Agnisys, full of events at the various technical exhibitions, new customers...

Semiconductor Register Specification: Shadow of a Shadow

So we have been working in the register specification space for a long time. We came out with the IDesignSpec...

Inroads into EDA using Machine Learning

Machine Learning (ML) is the rage these days and we were not untouched by it. Being   immersed in Specifications and...

Does UVM sometimes make you feel stupid?

Somewhere in the deep trenches of a UVM-based verification project, an engineer teeters on the verge of insanity...

How to Create Test Sequences for RISC-V Cores and SoCs Automatically

For decades, the idea of an open-source central processing unit (CPU) core was virtually unknown—let alone using it for commercial...

A pragmatic approach towards consolidation in the semi Industry

Consolidation is not a new phenomenon for the semiconductor Industry. Although the industry has shown no consolidation through almost all...

AUGER: Celebrating Our Users

In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in...
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