SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Begin Initialization Sequence – 10, 9, 8, …

OK rockets are not taking off yet, but we are excited to launch a new capability for our IDesignSpec suite...

Taking Stock of the Past Year

As we transition into 2023, it’s a good time to look back over the past year and assess it, much...

Efficient Design Automation Solutions: Meeting Industry Demands for Optimal Efficiency

The electronics industry’s current state intensifies demands on design, verification, and validation teams, requiring them to achieve more with fewer...

2015 Year End review – DV Challenges

Wow, what a marvelous year 2015 has been to Agnisys, full of events at the various technical exhibitions, new customers...

Semiconductor Register Specification: Shadow of a Shadow

So we have been working in the register specification space for a long time. We came out with the IDesignSpec...

Inroads into EDA using Machine Learning

Machine Learning (ML) is the rage these days and we were not untouched by it. Being   immersed in Specifications and...

Does UVM sometimes make you feel stupid?

Somewhere in the deep trenches of a UVM-based verification project, an engineer teeters on the verge of insanity...

How to Create Test Sequences for RISC-V Cores and SoCs Automatically

For decades, the idea of an open-source central processing unit (CPU) core was virtually unknown—let alone using it for commercial...
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