Three Smart Steps to Quickly Test a Register Map for Your Entire SoC
As I noted in a recent post, registers appear everywhere in system-on-chip (SoC) design. Architecturally defined registers form the hardware-software interface (HSI), where drivers, embedded software, and other code close to the hardware controls and monitors design functionality. The term “register map” describes the complete set of HSI registers and is an important part of the documentation for both chip designers and programmers. As with any part of your design, it is critical that you verify its proper operation before you spend millions of dollars to commit it to silicon. I’d like to offer three steps to accomplish this verification quickly and easily.
Establish an Executable Specification
You could say that there’s actually a “step zero” to this process: describing your registers in the form of an executable specification. As I hope you know by now, specification automation is what we do at Agnisys. We enable you to specify key parts of your designs—including registers—in executable format and we provide solutions that generate design, IP SoC verification, software, validation, and documentation files automatically from these specifications. Automation eliminates all the manual effort traditionally needed to create these files and update them every time that a specification changes.
So I’m assuming that you are specifying your registers in executable form and using our IDesignSpec GDI and IDS-Batch CLI solutions to generate the register-transfer-level (RTL) design for your registers (and memories too, if you wish). The RTL code we generate (in SystemVerilog, Verilog, VHDL, or SystemC) is all ready for simulation and synthesis. We also generate documentation in a variety of formats, which helps keep your development team in sync and gives your technical writers a great starting point for your user manuals. But we do much more to help you test your registers and verify that they work as you intended.
Step One: Generate Models, UVM Testbench, and Tests
Most of our users develop simulation testbenches complaint with the Universal Verification Methodology (UVM), so of course we support this standard. Along with the design and documentation, IDesignSpec GDI and IDS-Batch CLI generate UVM models for your registers. If you have an existing UVM testbench, you can plug these models in and use them immediately. That’s helpful, but many users would like us to generate a testbench ourselves to verify the registers. That’s where our IDS-Verify solution comes into play. We generate a complete UVM testbench and the tests necessary to verify that the RTL register design works properly.
This is harder than it might at first appear. Sure, we generate some fairly traditional tests used to read and write registers. However, we also generate hundreds of special register types, including indirect, indexed, read-only/write-only, alias, lock, shadow, FIFO, buffer, interrupt, counter, paged, virtual, external, read/write pairs, and combinations of these types. Every one of these requires special tests that go beyond the traditional. IDS-Verify generates all these tests and you can simulate them in the same testbench at the push of a button. If your register specification changes, you simply re-generate the tests and re-simulate. It’s all fully automated.
Step Two: Simulate Hardware and Software in Validation
Since your registers form the HSI, they can be accessed by software as well as the hardware in your SoC. It’s important to simulate the hardware and software together in pre-silicon validation to be sure that everything works together. IDS-Validate automates this process. It generates a validation environment in which the software runs on models of your embedded processors and interacts with your RTL design. We don’t just generate the framework; we also generate the actual C/C++ code that tests the registers from the software side of the HSI. Of course, we support all the special register types. If your specification changes, you can update the environment and code automatically.
When you get your chip back from the foundry and you’re in the bring-up lab, you need to perform post-silicon validation as well. The same C/C++ code that runs in simulation can also run on the actual processors in the actual SoC design in the lab. Further, programmers often incorporate our generated code into their production software such as drivers and embedded applications. The combination of ISD-Verify and IDS-Validate provides a complete, unified solution from high-level simulation all the way to silicon. Your same executable specification drives the entire process.
Step Three: Customize Verification and Validation for Unique Sequences
We’ve put a lot of thought into the tests we generate for registers, including all those special types. However, some users may have custom test sequences that they want to apply to their registers as well. Both IDS-Verify and IDS-Validate provide an intuitive way for you to specify your own sequences using an abstract scripting language with loops and other useful constructs. You can then generate both UVM tests and C/C++ code that include these sequences. If you change your executable sequence specification, the generated files also update automatically.
We offer many other options to customize this verification and validation flow. For example, the RTL that we generate for your registers includes an interface to the bus of your choice: APB, AHB, AHB-Lite, AXI4, TileLink, Avalon, Wishbone, or proprietary. The UVM tests we generate access the registers using this interface to ensure that all the registers in your SoC design are interconnected properly. As another example, the specification formats we support include SystemRDL, IP-XACT, JSON, RALF, YAML, XML, comma-separated value (CSV), and an interactive graphical editor.
Choose the Agnisys Solution
Fully automated IP SoC verification and validation are two of the many reasons why our IDesignSpec Suite goes far beyond traditional register automation tools and homegrown utilities. We would love to discuss your needs and show you how we can help. I invite you to contact us to schedule a discussion or demonstration with a member of our team to see how you can benefit from the industry’s best register automation solution.
