Will AI Eliminate Hardware-Software Interface Design?

 

When looking at emerging and rapidly expanding technologies, it can be hard to separate the reality, the potential, and the pure hype. Artificial intelligence (AI) is very much in this phase right now. AI has made amazing advances across many domains in recent years, but the predictions of what it will eventually be able to do are staggering. Yes, there is plenty of hype around, so it will take time to sort out what’s really possible and what will remain in the realm of science fiction.

AI and Chip Design

One domain of intense interest to Agnisys users is semiconductor development. Design, verification, programming, and validation of chips have become increasingly automated over the last few decades. This automation has obviated a lot of traditional manual effort. It is quite natural to wonder whether AI can bring this evolution to its full conclusion by completely replacing human engineers in one or more stages of development. 

Of all the chip development stages, register-transfer-level (RTL) design seems to be the one considered easiest for AI to tackle. It’s not hard to see how so many people reach this conclusion. Anyone can go to ChatGPT—or another AI tool using large language models (LLMs)—and type in “Generate SystemVerilog code for an 8-bit priority encoder.” The resulting RTL design looks quite reasonable:

Of course, the industry is a long way from auto-generating a complete system-on-chip (SoC) design. In addition, there are thorny legal issues of which data sets were used to train the LLM and what this means for IP rights and ownership of generated designs. Still, from a technology standpoint, it does seem clear that there are certain parts of a chip whose design can be completely automated by AI. Many development teams are taking their initial steps into AI-based design today.

AI for the HSI

One very important area of chip design is the hardware-software interface (HSI), which is required in any SoC, or even a complex IP block. The HSI is the mechanism by which low-level software configures and controls the hardware while reading back status. The hardware side of the HSI consists of memory-mapped, addressable control and status registers (CSRs). The software side consists of microcode, device drivers, and embedded operating systems and applications.

For well over a decade, designers have not had to hand-write RTL code for their CSRs. The Agnisys IDesignSpec™ Suite is a specification automation solution that generates register RTL code based on a wide range of executable formats, including SystemRDL and IP-XACT. Since they’re generated directly from the golden specifications, these designs are correct by construction. Whenever a CSR specification changes, the design can be updated immediately with no manual effort.

Recently, Agnisys introduced SmartDatasheet, which uses leading-edge LLM technology to analyze datasheets containing CSR definitions. SoC and IP datasheets invariably include register specifications in natural language form, which is usually not considered an executable format. However, by using natural language processing (NLP) and machine learning (ML), SmartDatasheet can read these specifications and create CSR definitions in standard executable formats.

AI + IDesignSpec: A Winning Combination

The executable CSR specifications created by SmartDatasheet are used by IDesignSpec to generate RTL for the registers, and memories as well. However, the registers alone do not form a complete CSR block. Interfaces are required, usually a system bus for access by the HSI software and an internal bus for connection to the rest of the chip. IDesignSpec generates any RTL bus interfaces needed, including APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, and Wishbone. 

In most cases, these buses operate on asynchronous clocks, and the registers may have their own third clock domain. IDesignSpec generates all clock-domain-crossing (CDC) logic needed to ensure metastability-free operation. Finally, users can ask IDesignSpec to add safety mechanisms such as parity, error-correcting code (ECC), cyclic redundancy check (CRC), and triple module redundancy (TMR) logic. These are often required to meet safety standards such as ISO 26262 and IEC 61508.

Thus, the combination of SmartDatasheet and IDesignSpec completely eliminates all manual RTL design effort for CSRs and memories, including bus interfaces, CDCs, and safety hardware. This innovative solution also helps with the software side of the HSI by automatically generating C/C++ headers for embedded programs and validation code. NLP and ML are also used to generate C/C++ register programming sequences from specifications written in natural language.

Summary

Whatever the likelihood of AI someday designing complete chips, today it adds value by automating the creation of register blocks from natural language specifications. This eliminates a big chunk of tedious manual effort, freeing designers to focus on the areas of the chip with higher differentiation value and more opportunities for innovation. Agnisys is an industry leader in harnessing the power of AI for SoC and IP development, so stay tuned for more exciting news going forward.