Semiconductor Design & Verification

  The Agnisys IDesignSpec™  Suite provides comprehensive clock domain crossing (CDC) circuitry support for both hardware and software. Key synchronization

Agnisys IDesignSpec™  optimizes low power design through advanced clock gating. By disabling the clock for inactive registers, IDS reduces dynamic

IDesignSpec™  enhances system reliability in safety-critical applications with features like SECDED, which corrects single-bit errors and detects two-bit errors, preventing

  Agnisys IDesignSpec™  facilitates seamless integration of various bus interfaces through automated generation of decoders and bridges, streamlining the design

  IDesignSpec™ provides robust support for complex structures and register types, enabling engineers to define intricate designs with remarkable flexibility.

Agnisys IDesignSpec™ streamlines the design process by interactively generating comprehensive output files tailored for design, verification, software, and documentation teams. From

  IDesignSpec™  empowers users with approximately 450 properties that enable extensive modification of the structure and behavior of generated outputs.

  The Agnisys IDesignSpec™ (IDS) suite offers powerful support for reading third-party data in various formats, including industry-standard formats like

  The Agnisys IDesignSpec™ Suite is certified for functional safety standards like ISO 26262 and IEC 61508, supporting all ASIL

  Maintaining a single golden specification is essential for consistency in chip development. Traditional workflows often lead to synchronization challenges

SystemRDL (System Register Description Language) plays an important role in the life cycle of System-on-Chip (SoC) development, facilitating efficient design,

Designing semiconductor devices has always been a distinct specialty of engineering, but today’s designers face immeasurably greater challenges. A typical

In SoC projects, where complex designs and architectures are the norm, having solid documentation is absolutely essential. It is important

In digital design, saving power is extremely important. It’s a top priority because it helps devices run efficiently. As electronic

The Universal Verification Methodology (UVM) has become a standard for verifying complex digital designs. One of the key components of

Introduction As our product portfolio has evolved over the last two decades, so has the capabilities of the various tools

IDesignSpecTM (IDS) is a product suite that improves the productivity of FPGA/ASIC, IP/SoC, and System Development teams. These products encompass

Formal verification is a crucial aspect of ensuring the reliability and safety of systems. ARV stands for Automatic Register Verification.

Late last year, I published a blog post that summarized what had transpired for Agnisys over the course of 2021.

The Intersection of Functional Safety and Electronic Design In an industry that has gone through an incredibly rapid transformation over

The Agnisys IDesignSpec™ Suite offers development teams a closely linked set of products, including a unified graphical design interface (GDI)

The UVM register model is an essential component of the UVM-based verification for modern designs. In this article, we discuss

In the ever-evolving landscape of semiconductor and electronic design, the pursuit of efficiency, consistency, and reusability remains paramount. Designers frequently

In system design, engineers grapple with two formidable challenges: the relentless miniaturization of technology nodes and the ever-pressing demand for

Machine learning has begun to have a huge impact on the EDA Industry. Numerous organizations are heading forward with homegrown

The two biggest challenges of today’s complex design are IP-Integration and Verification, and we would like to address solution scoping

As we transition into 2023, it’s a good time to look back over the past year and assess it, much

Machine Learning (ML) is the rage these days and we were not untouched by it. Being   immersed in Specifications and

Consolidation is not a new phenomenon for the semiconductor Industry. Although the industry has shown no consolidation through almost all

Introduction

Improved technology for remote learning emerged as one positive outcome amid the challenges of the last year and a half. 

Hardware is verified using simulators. Software compiled and debugged using compilers and debuggers. When it comes to the hardware/software interface,

We all have different tastes and different habits and when it comes to work we like to work in different

I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series

Navigating SoC Complexity System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design,

Modern RTL design verification (DV) environments are both compelling and very complex. They include advanced simulation testbenches plus support for

Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM).

Introduction As per the IP-XACT User Guide, IP-XACT defines an API called Tight Generator Interface (TGI) to query, modify, create,

Typically thousands of registers are required for today’s complex designs, which are used to control the operations of the SOC.

It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology

As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate

Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one

A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based

Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC)

Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But

Ask a bunch of engineers about the Universal Verification Methodology (UVM) and you’ll hear two distinct sets of responses, sometimes

The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed

As we close in on the final days of 2021, I can’t help but think back over the events of

This was an intriguing DAC. Hardware-Software Interface (HSI) is increasingly emerging as an area of importance, and because of this

Participating in DVCon has always been a wonderful experience for us as an organization. We had a great response and

  In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has

Verification and Validation are two sides of the same coin

  In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars

Introduction

  As an electronic design automation (EDA) company, Agnisys provides many benefits for chip design and verification engineers. Our specification

Agnisys will showcase IDesignSpec NextGen – the Next Generation product for  capturing requirement specification for embedded designs, and automatically  generating

After almost a decade of focusing on SV, UVM, SystemC to build software products and teaching advanced verification/modeling to hordes

Agnisys has customers designing all sorts of intellectual property (IP) blocks, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and

The DVCon Conference this year, was quite eventful for us with a lots of visitors at our booth. We were

  DVCon 2014 was a wrap. It was marked by record attendance and participation both by the DV Community and

Started blogging again, this time from our own blogging site.

The Design Automation Conference is over for the year. Attendee leads or inquiries, to be more precise, have been collected

Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular.

Most engineers involved in the design, verification, and validation of electronic systems are familiar with the Design Automation Conference (DAC).

Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference

In engineering, we often go about our work not knowing how that work touches others’ life and society in general.

Why Machine Learning Matters Machine learning (or “ML” for short) may have begun life as something of a buzzword, but

I’m yet to meet a person who doesn’t like simplicity in engineering. I do believe that   Electronic Design Automation (EDA)

The input format of Duolog is now supported by IDesignSpec with outputs including Verilog, UVM, CHeader, and SystemC. The outputs generated

Hardware design verification consumes more than 60% of resources, often more than that. These resources are not just engineers but

San Francisco, CA. June 2nd, 2014 – Agnisys, Inc. Launches DVInsight™, an Integrated Development Environment (IDE) for creating SystemVerilog (SV)

In our first Newsletter of 2022 we are drawing your attention to new capabilities in the IDesignSpec family of products.

Happy New Year 2021 to you all !!! With the new year, Agnisys tools have an amazing set of enhancements.

In this newsletter, you will find articles about the basic differences between Paged registers and Alternate register, Auto-Mirroring for volatile