UPCOMING EVENTS
February 24-27, 2025
DVCon US
The Design & verification conference and Exhibition is the premier conference on the application of languages, tools and methodologies and standards for the design and verification of electric systems and integrated circuits.
Visit with Agnisys, the Industry Leader in Golden Executable Specification Solutions™, in booth #123
Agnisys automates design, verification, and validation by capturing and centralizing registers, sequences, and connectivity for your IP and SoC development projects. Our solutions team can show you how to leverage IP-XACT, PSS, SystemRDL, YAML, Word, and Excel templates to dramatically increase productivity and reduce risk.
Webinar
AI Chip Design Using Agnisys
The design of AI chips hinges on optimizing performance for computationally heavy operations like Multiply-Accumulate (MAC), a core component of neural network workloads.
To meet the demands of speed and energy efficiency, AI chip architectures increasingly integrate advanced techniques like systolic arrays, parallel processing, and domain-specific accelerators. Agnisys tools contribute significantly to this ecosystem by automating key steps in chip design and verification.
For instance, IDesignSpec (IDS) enables efficient generation of RTL for registers and memories while supporting multiple bus standards. These capabilities streamline the transition from specification to implementation, minimizing errors and accelerating time-to-market. With a suite that leverages neuromorphic chips, 3D stacking, and edge-specific processors to address emerging AI use cases like IoT and robotics.
Together, these advancements push the boundaries of AI computing while maintaining a focus on precision, reliability, and innovation. Register For Free Webinar
Older Events
Webinar
Optimizing Hardware Design with SystemRDL: Tools, Techniques, and Tips
Efficient register and memory map management is vital for today’s complex System-on-Chip (SoC) designs. In this webinar, discover how Agnisys’s IDesignSpec Suite leverages SystemRDL to automate design, verification, and integration processes. Learn best practices, explore real-world use cases, and see how IDesignSpec enhances efficiency, reduces errors, and ensures compliance with industry standards, transforming your SoC development workflow.
Don’t miss this opportunity to see how Agnisys’s IDesignSpec Suite can revolutionize your SoC development with the power of SystemRDL!”
Webinar
Advantages of using IP-XACT and TGI for SoC Development
SoC development involves managing registers, integrating IPs, and ensuring collaboration across teams, often leading to iterative rework. IP-XACT, an IEEE standard by Accellera, streamlines workflows by standardizing data exchange and enabling automation. The latest IP-XACT 2022, with its TGI API, simplifies design processes, enhances efficiency, and reduces development cycles. This webinar will demonstrate how to leverage IP-XACT for optimized resources, seamless integration, and faster time-to-market.
August 29, 2024
DVCon Japan
The Design and Verification Conference is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. Agnisys, the pioneer and industry leader in Golden Executable Specification Solutions™ will be presenting a paper at DVCon Japan titled, “Auto Gen of Embedded System Layer using PSS and System RDL” in Room 3 from 14:15 to 14:45. Learn how our certified IDesignSpec™ Solution Suite leverages a golden executable specification to capture and centralize registers, sequences, and connectivity for Intellectual Property (IP) and System-on-a-Chip (SoC) projects. We help market makers accelerate their front-end SoC, FPGA, and IP development – let us help you ensure your project success!
September 18-19, 2024
DVCon India
Agnisys will be showcasing at the Design and Verification Conference in India, this will be held on 18-19th September 2024 as an In-Person conference. The conference will follow the contemporary Indian version of a two-day conference with in-depth technical content spread across both days. This 9th conference will be the pinnacle of innovation, collaboration and insight.
March 4-7, 2024
DVCon US
The Design & verification conference and Exhibition is the premier conference on the application of languages, tools and methodologies and standards for the design and verification of electric systems and integrated circuits.
Visit with Agnisys, the Industry Leader in Golden Executable Specification Solutions™, in booth #103.
Agnisys automates design, verification, and validation by capturing and centralizing registers, sequences, and connectivity for your IP and SoC development projects. Our solutions team can show you how to leverage IP-XACT, PSS, SystemRDL, YAML, Word, and Excel templates to dramatically increase productivity and reduce risk.
June 23-27, 2024
DAC 2024
Agnisys is excited to participate in the 61st Design Automation Conference (DAC) 2024, taking place from June 23 to 27, at the Moscone West in San Francisco, CA.
At Booth #2457, we will showcase our latest automation solutions designed to enhance the efficiency and performance of complex hardware systems. We are also proud to sponsor
the “I LOVE DAC” program, offering 44 Engineering Track promo codes on a first-come, first-served basis. Additionally, Agnisys will present at the Exhibitor Forum on “Object Oriented Embedded Hardware for Operational Excellence.” Join us to explore innovative methodologies in embedded hardware design, engage with our experts, and benefit from valuable learning opportunities at DAC 2024. Participate in our design contest, you will discover how easy it is to use IDS-NG for creating digital designs.
April 25, 2024
IP SoC Silicon
Valley 24
Agnisys will participate in the IP-SoC Silicon Valley 24 organized by Design-and Reuse, where innovations will be discussed around IP and SoC solutions.. As a leading provider of innovative solutions for semiconductor design automation, Agnisys experts will present the latest in IP and SoC development.
Agnisys invites you to visit booth #15 at the IP-SoC Silicon Valley 24 to engage with its team of experts, explore live demonstrations, and discover firsthand how to develop IP/SoC faster, better, cheaper using its unique products. We will also present a talk about how we are able to achieve fastest development by “Automatic generation of Device Driver and Programmer’s Reference Manual from PSS”.
