Silicon IP Portfolio
Silicon IP Portfolio
Comprehensive Silicon-Proven IP Portfolio for Efficient SoC Design
AMBA APB Target
Definition
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Features
- Wait state
- Error reporting
- Transaction protection
- Sparse data transfer
- Flopped and non-flopped
- Synchronous or asynchronous reset type
- APB 4 / APB3
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
AMBA AHB Target
Definition
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
Features
- AHB3 Lite and Full featured
- Burst transfers supported
- Single clock-edge operation
- Non-tristate implementation
- Flopped and non-flopped outputs
- Synchronous or asynchronous reset type
- Low Data Latency
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
AMBA AXI Target
Definition
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs “channels” to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
Features
- Independent read and write channels
- Multiple outstanding addresses on single ID
- Support for unaligned data transfers
- Out-of-order transaction completion
- Burst transactions based on start address
- Flopped and non-flopped
- Synchronous or asynchronous reset type
- AXI4 lite, AXI4 full, and AXI5 lite
- Low Data Latency or wait stages
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
Wishbone Target
Definition
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its goal is to promote design reuse by addressing system-on-chip integration issues. This is accomplished by providing a standard interface for IP cores. This increases the system’s mobility and stability, resulting in a shorter time-to-market for end users.
Features
- Flopped and non-flopped
- Synchronous or asynchronous reset type
- Supports single clock data transfers
- Data Latency or wait stages
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
Avalon Target
Definition
Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs. The Avalon interface family defines interfaces that can stream high-speed data, read and write registers and memory, and operate off-chip devices. Platform Designer components incorporate these standard interfaces. Furthermore, you can include Avalon APIs in custom components, increasing the interoperability of designs.
Features
- Synchronous or asynchronous reset type
- Supports single clock data transfers
- Data Latency or wait stages
- Burst and non-burst transfers
- Byte enabling
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
TileLink Target
Definition
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. TileLink is intended for use in a System On-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complicated devices, utilising a fast, scalable interconnect that provides both low latency and high-throughput transfers.
Features
- TL-UL both 1.7 and 1.8 standard
- TL-UL: ‘PutFullData’, ‘PutPartialData’, ‘Get’, ‘AccessAck’, ‘AccessAckData’ and Error response
- All three messages above, with and without latency transaction
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
Bus Decoders
Definition
Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus transaction. It also produces error messages for empty addresses in the hierarchy.
Supported Bus
- APB
- AHB
- AXI
- TileLink
Features for Supported Buses
- Flopped and non-flopped
- Third party IPs integration
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
Bus Bridges
Definition
Various bus types of protocols are available and employed in many applications, all of which require a bridge to operate safely and without loss of data. SoC is essentially a system made up of components and their interconnections. Recently, the development of SoC chips with reusable IP cores has received more attention due to their lower cost and shorter time to market. The communication between the several IP cores should be lossless and designer-friendly.
Supported Bus Bridges
- AXI4-Lite/AXI4 to APB
Features
- Independent read and write channels.
- Burst transfers.
- Single clock-edge operation.
- Non-tristate implementation.
- Synchronous or asynchronous reset type.
- Data Latency or wait states.
- AHB3-Lite/ AHB3 to APB
Features
- Burst transfers.
- Single clock-edge operation.
- Non-tristate implementation.
- Synchronous or asynchronous reset type.
- Data Latency or wait states.
- AHB3 to AXI4-Lite/AXI4
Features
- Burst transfers.
- Single clock-edge operation.
- Non-tristate implementation.
- Synchronous or asynchronous reset type.
- Data Latency or wait states.
- AXI4-Lite/AXI4 to AHB3-Lite
Features
- Independent read and write channels.
- Burst transfers.
- Single clock-edge operation.
- Non-tristate implementation.
- Synchronous or asynchronous reset type.
- Data Latency or wait states.
- Tilelink 1.8 to APB
Features
- Independent read and write channels.
- Synchronous or asynchronous reset type.
- Data Latency or wait states.
Bus Convertors
Definition
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes.
- APB: 32-bit wide initiator data buses to 16-bit target data buses.
- AHB: 64-bit wide initiator data buses to 32-bit target data buses.
- AXI: 256-bit wide initiator data buses to 64-bit target data buses
A wide target on a narrow bus, only requires external logic and no internal design changes.
- APB: 16-bit wide initiator data buses to 32-bit target data buses.
- AHB: 32-bit wide initiator data buses to 64-bit target data buses.
- AXI: 64-bit wide initiator data buses to 256-bit target data buses.
Features
- TL-UL both 1.7 and 1.8 standard
- TL-UL: ‘PutFullData’, ‘PutPartialData’, ‘Get’, ‘AccessAck’, ‘AccessAckData’ and Error response
- All three messages above, with and without latency transaction
Configurability
Agnisys provides a tool – IDesignSpec to configure the IP.
Crossbars Interconnect
Definition
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
Supported Bus
- APB
- AHB
- AXI
Features for Supported Buses
- Up to 16 initiators interface and 8 target interfaces.
- Fixed priority arbitration.
- 32-bit data width for APB and AHB.
- 64-bit data width for AXI.