IP-XACT
IP-XACT
Today’s huge, complex system-on-chip (SoC) designs are composed of hundreds or thousands of intellectual property (IP) blocks. SoC designers obtain this IP from commercial IP suppliers, electronic design automation (EDA) vendors, foundries, open-source repositories, development partners, and reused logic from their own previous generations of chips. Integration of this diverse IP into a single coherent design is a challenge, and one important part of the solution is a way to describe and document blocks. The Intellectual Property exchange – Abstract Core Technology (IP-XACT) standard is the best way to accomplish this.
IP-XACT Is a Well Established Format
The industry’s need for a consistent IP descriptive format was the driver for the development of IP-XACT by the SPIRIT Consortium, now part of the Accellera Systems Initiative standards organization. It is also an IEEE standard (1685-2022) so it is clearly well accepted and widely adopted. It is an XML-based standard that makes it easier to evaluate IP offerings and integrate them into SoC designs. Its core objectives are:
Defining a consistent framework for IP representation
Ensuring compatibility among diverse IP descriptions from multiple vendors
Enabling exchange of IP libraries between EDA design and verification tools
Providing detailed depiction of configurable IP through metadata
Facilitating EDA-vendor-neutral IP creation, generation, and configuration scripts
Many leading companies follow the IP-XACT standard for defining and describing SoCs/systems, bus interfaces and connections, bus abstractions, and IP details such as address maps, register and field descriptions, and file set descriptions. These descriptions are used to automate architectural design, register-transfer-level (RTL) design, verification, validation, and documentation flows for electronic systems of all kinds. Many EDA vendors support the standard in a wide range of tools that enable these flows for both IP and SoC projects.
IP-XACT Has Powerful Capabilities
IP-XACT provides a standardized XML schema for describing and IP at multiple levels of abstraction. The standard encompasses a comprehensive set of metadata, configuration details, and hierarchical structures, making it a robust and flexible way to describe diverse IP for many purposes. The XML schema is fully compliant with World Wide Web Consortium (W3C) standards and augmented by semantic consistency rules (SCRs).
Additionally, IP-XACT offers a portable generator interface that seamlessly traverses tool flows from multiple EDA vendors. The combination of methodology-independent metadata and the tool-independent mechanism for accessing that data enables the portability of design data, design methodologies, and environment implementations.
IP-XACT has the potential to provide great benefits to project teams, but its ability to provide these benefits depends on the quality of the descriptions. The quality of IP-XACT documents has a direct impact on the reliability and effectiveness of IP integration efforts. It involves adhering to best practices and guidelines defined by the IP-XACT standard, which encompass accurate metadata, correct configurations, and precise hierarchical structuring. Maintaining high IP-XACT quality is not only an industry best practice but also a critical element in the pursuit of efficient and trouble-free IP integration in diverse SoC projects.
IP-XACT Is a Great Way to Define Registers
Defining the addressable registers in an IP or SoC design is one of the most popular applications for the IP-XACT standard. These registers form part of the hardware-software interface (HSI), the mechanism by which drivers and embedded software configure the hardware, control its operation, and gather status. This means that many teams use the same register definitions: RTL designers; embedded programmers; verification, validation, and bringup engineers; and technical writers. Sharing a common, unambiguous, executable register description is essential.
IP-XACT is especially valuable when coupled with a register automation solution. If EDA tools can generate the RTL design, C/C++ code, UVM-based verification and validation environments, and high-quality documentation from the IP-XACT description then all teams are aligned. Register details such as location, type, and bitfields change many times over the course of a project. Whenever this happens, output files are simply regenerated so that the teams remain in sync. This saves time and resources at multiple points in the schedule while avoiding the debug effort associated with inconsistency.
IP-XACT Is a Great Way to Describe IP
In addition to the addressable registers and their memory map, IP-XACT provides the capabilities to describe many attributes of an IP block. These include memories, ports, interfaces, and instances. The latest release of the standard added support for power domains, analog/mixed-signal (AMS) properties, and runtime configurable parameters for models of the IP. Ongoing standardization work will make it possible to include clock domain crossing (CDC) information as well.
There are some significant advantages to using IP-XACT to define IP attributes rather than other formats such as SystemRDL:
- IP-XACT fully supports registers, but its scope extends far beyond formats defined only for register and memory definition
- Because of its wide support among IP and EDA vendors, IP blocks can be easily reused across different designs, projects, and organizations without the need for manual edits
- IP-XACT enjoys strong industry support and is compatible with a wide array of EDA tools, fostering interoperability with diverse tools and environments.
- The standardized structure of IP-XACT streamlines the integration of IP, with the block-level metadata and register descriptions seamlessly integrated into the overall design
- IP-XACT promotes comprehensive IP documentation, including detailed register descriptions and their associated properties, simplifying communication of IP-related information
- As design environments and tools continue to evolve, having register descriptions in IP-XACT is strategically advantageous, future-proofing the IP
Agnisys Provides The Best IP-XACT Register Solution
The Agnisys IDesignSpec™ (IDS) Suite leverages all the power of IP-XACT in its specification automation solution for registers and other aspects of IP and SoC design. IDesignSpec GDI and IDS-Batch™ CLI read in IP-XACT descriptions and automatically generate synthesizable RTL designs, Universal Verification Methodology (UVM) models and verification environments, C/C++ header files, and documentation good enough for inclusion in user manuals.
IDS supports hundreds of special register types, including indirect, indexed, read-only/write-only, alias, lock, shadow, FIFO, buffer, interrupt, counter, paged, virtual, external, read/write pairs, and combinations of these. Some of these types go beyond the scope of the current IP-XACT standard, so Agnisys makes use of the vendor extension (VE) mechanism. This provides maximum user flexibility while staying fully compliant with the standard. IDS verifies the generated RTL code for all these register types to ensure that the design is correct by construction.
Another aspect of user flexibility is that IDS accepts register definitions in a variety of formats, including SystemRDL, spreadsheets, and an intuitive graphical register editor. For all these inputs, IDesignSpec GDI and IDS-Batch CLI generate IP-XACT output files to make it easy to interact with other IP blocks and EDA tools supporting the standard. This satisfies the goal of making design reuse as easy and efficient as possible.
Agnisys Provides The Best IP-XACT Integration Solution
IDS-Integrate™, also part of the IDS Suite, is based on the IP-XACT standard. It can read IP-XACT descriptions of third-party IP blocks in addition to those blocks generated by IDesignSpec GDI, IDS-Batch CLI, and the IDS-IPGen™ configurable library. Since many IP vendors provide IP-XACT descriptions as part of their product documentation, this enables IDS-Integrate to directly support available IP in the market with no user effort.
SoC designers specify in Tcl or Python how the blocks should be interconnected. IDS-Integrate assembles all IP blocks from all sources into a complete top-level SoC RTL design based on this specification, and can:
Read the IP-XACT description for a third-party block and connect it to existing blocks
Connect an IDS-generated block to a custom block and create a wrapper around it
Connect an AHB bus to an APB slave by automatically instantiating a bridge
Connect several AHB blocks to an AHB master by automatically instantiating an aggregator
Move a block from inside a deep hierarchy several levels higher
Generate a merged IP-XACT description for the full SoC
Generate a block diagram of the full SoC, showing all IP blocks
Generate SystemVerilog Assertions (SVA) for connectivity checks using formal verification
Agnisys and IP-XACT: The Way to Go
With modern SoCs incorporating hundreds of thousands of IP blocks from diverse sources, a consistent way to describe the IP registers and integrate them into the full chip is essential. IP-XACT is central to this process, and Agnisys fully supports this standard. In fact, IDesignSpec GDI, IDS-Batch CLI, and IDS-Integrate go well beyond the capabilities of other EDA tools by automatically generating many critical output files. This benefits all the teams on an IP or SoC project, shortening the schedule, saving precious engineering resources, and keeping all teams in sync at all times.
