In our recent Formal Verification webinar explored the crucial role of rigorous verification in ensuring hardware design reliability amidst increasing complexity. We showcased iSpec.ai, leveraging advanced LLMs and innovative techniques like Prompt Engineering and Fine-Tuning to streamline SystemVerilog Assertion generation from plain English requirements. By bridging machine translation with formal verification, iSpec.ai offers a transformative solution to address time-to-market challenges and mitigate risks associated with traditional verification methods.