IDesignSpecTM : Automatic code generation from register specifications

Fosters team-based design while eliminating hardware-software integration errors
Automatic code generation for UVM, OVM, VMM, RTL, C/C++ headers etc.

IVerifySpecTM enables you to create collaborative, self updating, vendor neutral, Verification Plans
that improve team collaboration, eliminate verification holes and speed up verification closure.

    

Agnisys offers a suite of affordable VLSI design and verification tools for SoC, FPGAs and IP design that enhance collaboration, design re-use and enable productive team-based development methods. Our mission is to equip your design team with high impact hardware-software test and development tools that streamline collaboration and enhance integration testing for your advanced VLSI design projects.

IDesignSpecTM automates creation of register and memory maps guaranteeing higher quality and consistent results across hardware and software team members. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized. Register verification and register management consumes up to 20% of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds.

IVerifySpecTM is a solution for verification planning and audits that exposes verification holes driving faster verification closure and achieving code coverage for VLSI and FPGA design projects that span multiple teams and disciplines. IVerifySpec provides direct visibility and mapping between tests and specifications enabling teams and management to see which product features are affected by failing regression tests. This traceability between tests and specifications aids integration testing while enabling verification teams to achieve verification closure in less time.

IAssertSpecTM eases the adoption of assertion based VLSI design verification methodologies by guiding assertion development while ensuring the assertions are consistent with the design specifications.

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Feb 27th - March 1st 2012

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