IC DEVELOPMENT RESOURCE CENTER
Resource
Podcast
The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys
Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry.
Webinar
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
Learn about front-end automation advances that leverage an innovative register information management system for the capture and centralization of hardware functionality.
Interview
D&R Interview at DAC 23
D&R Interview at DAC 23 with Anupam Bakshi - Founder & CEO at Agnisys, Inc.
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Webinar
IP-XACT 2022 - What's New?
This webinar will highlight some of the capabilities of IP-XACT 2022 in Agnisys tools. We will offer a brief introduction to the IP-XACT standard for users who are new to it. Therefore, participating in this webinar will be beneficial for both new users and seasoned users of IP-XACT.
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Webinar
Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
This webinar will examine the techniques used to avoid metastability as signals cross from one clock domain to another.
Webinar
Auto-generation of Verification Infrastructure for IP to SoC
Explore the Agnisys Tool's capabilities in the Automatic Generation of Verification Infrastructure for IP/SoC. Our webinar offered a concise yet insightful overview of how Agnisys simplifies the generation and verification of infrastructure for IP/SoC development. Additionally, we provided a brief insight into the custom glue logic generator and the validation of IP/SoC, delivering benefits for both validation and verification engineers.
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Webinar
Verifying Safety in Automotive
In our webinar, we discussed essential safety mechanisms and security measures in automotive and avionics, including ISO 26262 and DO-254 standards. We explored parity, CRC, SECDED, TMR, error injection, and security methods like locks, AES encryption, and bus protection, applicable across various industries.
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eBook
The IC Designer’s Guide to Automated Specification of Design, Verification, and Validation for Better Products
There are multiple causes for designs being wrong, but some of the most common are related to the design specifications and how they are distributed and maintained throughout the product development lifecycle. Learn how to address this issue by reading this guide.
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eBook
Using PSS for Sequence Specification and Generation
Specification automation is an important technology that spans many aspects of intellectual property (IP) and system-on-chip (SoC) development. From executable specifications, electronic design automation (EDA) tools automatically generate many diverse types of files used for the design, verification, programming, validation, and documentation of IP and SoC projects.
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eBook
How Agnisys Eliminates Redundancies in Semiconductor Design, Verification and Validation
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.
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Webinar
Formal Verification
Case Study
The Benefits Discretix Gained With IDesignSpec™
IDesignSpec™ changes the way Discretix develops embedded security solutions and IP solutions.
Presentation
Specification Automation for IP/SoC Design, Verification, Firmware and Documentation
Specification Automation for IP/SoC Design, Verification, Firmware and Documentation at DVCon US 2022
Case Study
How Xingtera Created a Fast and Efficient Design Process With IDesignSpec
Learn how IDesignSpec helped the company improve their semiconductor design productivity significantly.
Presentation
Automating IP and SOC Verification
Learn about the challenges and opportunities for verification of IP and SoCs
Case Study
Customer interview with Allegro Microsystems
In this video customer interview, learn how Allegro Microsystems uses and benefits from Agnisys products.
Case Study
Customer Interview with Analog Inference
In this video customer interview, learn how Analog Inference uses and benefits from Agnisys products.
Case Study
Customer Interview with Yellowbrick
In this video customer interview, learn how Yellowbrick benefits from Agnisys products.
Presentation
Designing IP and Device Driver for RISC-V
Developing and integrating IPs and device drivers with processor cores based on RISC-V is a daunting task that requires a lot of automation and expertise.
Presentation
Auto-generate Implementation-level Sequences for Portable Stimulus Tools
Presentation about auto-generate implementation-level sequences for portable stimulus tools.
Whitepaper
Using Machine Learning in Register Automation and Verification
In this paper, understand how machine learning can be applied to register automation and verification.
Whitepaper
In pursuit of Faster Register Abstract Layer (RAL) Model
Podcast
Agnisys joins Amelia Dalton’s Virtual Verification Smorgasbord Fish Fry
In this week’s Fish Fry, we’re gobbling down as much verification as we possibly can fit on our podcastin’ plate.
Interview
Interview with EDA Cafe at DAC 2018!
Sanjay Gangal interviews Anupam Bakshi, Agnisys Founder & CEO
Video
IDesignSpec : Register Generator
IDesignSpec is a Register Generator tool that enables you to quickly generate high-quality code right from your document editor.
Video
Verifying Registers using UVM and IDesignSpec
This video shows how IDesignSpec can be used to generate register models, customize the generated models and how to simulate and verify the registers in the design.
Video
Specification to Realization from Agnisys to Xilinx Zedboard
Target Xilinx Zedboard and the Zync FPGA using Agnisys tools: IDesignSpec and ISequenceSpec for fastest Specification to Realization.
Video
DVinsight – Design Verification Editor Checker for SV/UVM
DVinsight is a smart editor for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code.
Video
Agnisys Product Overview
An overview of innovative software that solves complex design and verification problems for system development.
Interview
D&R Interview at DAC 22
D&R Interview at DAC 22 with Anupam Bakshi - Founder & CEO at Agnisys, Inc.
Webinar
Introduction to System RDL Part 1
SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs.
Webinar
Introduction to System RDL Part 2
SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs.
Webinar
IDesignSpec GDI for Safety-Critical Designs
In this webinar we discussed how the IDesignSpec GDI FS tool helps teams to develop Functionally Safe designs.
Whitepaper
Key Gochas in implementing CDC for various Bus Protocols
The paper will talk about the simulation results obtained for the implementation of a low power RTL design and techniques used for interconnection with various bus protocols.
Whitepaper
AI Based Sequence Detection
The article talks about the current state of development and gives ideas about how the reader can implement their own solution to achieve true specification driven software development.
Case Study
CERN Selects Agnisys IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider
Learn how CERN uses Agnisys IDesignSpec for The TOTEM Experiment Project
Case Study
Allegro Selects Agnisys IDesignSpec™ and ARV-Sim™ for Specification Creation, Automatic HDL and UVM Model Generation for Register and Memory Blocks
Learn how Allegro uses Agnisys IDesignSpec™ for Specification Creation, Automatic and UVM Model Generation.
Webinar
IDS-NG for Formal Verification
In this webinar we discuss the importance of auto-generating System Verilog Assertions
Webinar
IDS- NG for system verification
This webinar discusses verification and validation of SoCs in general and specifically with IDS-NG.
Webinar
IDS- NG for documentation
Chip/IP documentation is a critically important resource to save project time and effort.
Webinar
IDS-NG for Firmware
A sequence is an ordered set of transactions on various interfaces/ports of a device.
Webinar
Centralized Register Design and Verification from a Golden Specification
How to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec.
Webinar
IP Connectivity and Smart Assembly Methodology for SoCs
How to automatically assemble and connect IPs from many different sources at your SoC level using SoC Enterprise.
Webinar
From Cross-Platform Specification to Code Generation at the Enterprise Level
Capture your register and sequence specifications for IPs and SoCs from the individual IP to the enterprise level using IDS-NextGen.
Webinar
A Complete UVM Automated Based Verification System
Automatically generate a complete UVM testbench for your addressable registers and application logic, including sequence items, configurations, checkers, coverage, and even the UVM plumbing, using Specta-AV™.
Webinar
Automatic Creation of Pre Validated RTL for Highly Configurable IPs
How to automatically generate IPs designed to be easily customizable and configurable to meet your SoC requirements using the SLIP-G.
Webinar
System-Level Validation with RISC-V Processors
How to stimulate your RTL design with synchronized SoC testbench and RISC-V embedded tests using Automatic SoC Verification and Validation (ASVV™).
Webinar
An Easy Solution for Automated Register Verification
How to stress-test your registers in simulation by automatically generating your entire UVM testbench and supporting Make files for complete register verification using ARV-Sim.
Case Study
The Benefits Discretix Gained With IDesignSpec™
Case Study
How Xingtera Created a Fast and Efficient Design Process With IDesignSpec
Case Study
Customer interview with Allegro Microsystems
Case Study
Customer Interview with Analog Inference
Case Study
Customer Interview with Yellowbrick
Case Study
CERN Selects Agnisys IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider
Case Study
Allegro Selects Agnisys IDesignSpec™ and ARV-Sim™ for Specification Creation, Automatic HDL and UVM Model Generation for Register and Memory Blocks
Learn how Allegro uses Agnisys IDesignSpec™ for Specification Creation, Automatic and UVM Model Generation.
eBook
How to Reduce Semiconductor Design Errors Caused by Inconsistent Specifications
This eBook highlights how traditional semiconductor development leads to inefficiencies and delays due to manual processes. Specification automation addresses these challenges by generating consistent, correct designs from executable golden specifications. Agnisys, the industry leader, offers a complete solution for registers, sequences, IP blocks, and block integration, significantly improving efficiency and time-to-market.
eBook
The IC Designer’s Guide to Automated Specification of Design, Verification, and Validation for Better Products
There are multiple causes for designs being wrong, but some of the most common are related to the design specifications and how they are distributed and maintained throughout the product development lifecycle. Learn how to address this issue by reading this guide.
eBook
Using PSS for Sequence Specification and Generation
Specification automation is an important technology that spans many aspects of intellectual property (IP) and system-on-chip (SoC) development. From executable specifications, electronic design automation (EDA) tools automatically generate many diverse types of files used for the design, verification, programming, validation, and documentation of IP and SoC projects.
eBook
How Agnisys Eliminates Redundancies in Semiconductor Design, Verification and Validation
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.
Interview
D&R Interview at DAC 23
Interview
Interview with EDA Cafe at DAC 2018!
Interview
D&R Interview at DAC 22
Podcast
The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys
Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry.
Podcast
Agnisys joins Amelia Dalton’s Virtual Verification Smorgasbord Fish Fry
Presentation
Specification Automation for IP/SoC Design, Verification, Firmware and Documentation
Presentation
Automating IP and SOC Verification
Presentation
Designing IP and Device Driver for RISC-V
Presentation
Auto-generate Implementation-level Sequences for Portable Stimulus Tools
Video
IDesignSpec : Register Generator
Video
Verifying Registers using UVM and IDesignSpec
Video
Specification to Realization from Agnisys to Xilinx Zedboard
Video
DVinsight – Design Verification Editor Checker for SV/UVM
Video
Agnisys Product Overview
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Webinar
AI/ML in verification
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Webinar
Optimizing Hardware Design with SystemRDL: Tools, Techniques, and Tips
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Webinar
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development
Webinar
IP-XACT 2022 - What's New?
Webinar
Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
Webinar
Auto-generation of Verification Infrastructure for IP to SoC
Webinar
Verifying Safety in Automotive
Webinar
Formal Verification
In our recent Formal Verification webinar explored the crucial role of rigorous verification in ensuring hardware design reliability amidst increasing complexity. We showcased iSpec.ai, leveraging advanced LLMs and innovative techniques like Prompt Engineering and Fine-Tuning to streamline SystemVerilog Assertion generation from plain English requirements. By bridging machine translation with formal verification, iSpec.ai offers a transformative solution to address time-to-market challenges and mitigate risks associated with traditional verification methods.
Webinar
Introduction to System RDL Part 1
Webinar
Introduction to System RDL Part 2
Webinar
IDesignSpec GDI for Safety-Critical Designs
Webinar
IDS-NG for Formal Verification
Webinar
IDS- NG for system verification
Webinar
IDS- NG for documentation
Webinar
IDS-NG for Firmware
Webinar
Centralized Register Design and Verification from a Golden Specification
Webinar
IP Connectivity and Smart Assembly Methodology for SoCs
Webinar
From Cross-Platform Specification to Code Generation at the Enterprise Level
Webinar
A Complete UVM Automated Based Verification System
Webinar
Automatic Creation of Pre Validated RTL for Highly Configurable IPs
Webinar
System-Level Validation with RISC-V Processors
Webinar
An Easy Solution for Automated Register Verification
Webinar
Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™
Whitepaper
Using Machine Learning in Register Automation and Verification
Whitepaper
In pursuit of Faster Register Abstract Layer (RAL) Model
This paper introduces the new approaches for register layer. These models are developed in order to overcome the performance issues of the traditional UVM RAL model.
Whitepaper
Key Gochas in implementing CDC for various Bus Protocols
The paper will talk about the simulation results obtained for the implementation of a low power RTL design and techniques used for interconnection with various bus protocols.
Whitepaper
AI Based Sequence Detection
The article talks about the current state of development and gives ideas about how the reader can implement their own solution to achieve true specification driven software development.
